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ADS1147IPWR Arkusz danych(PDF) 3 Page - Texas Instruments

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Numer części ADS1147IPWR
Szczegółowy opis  16-Bit Analog-to-Digital Converters for Temperature Sensors
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ADS1147IPWR Arkusz danych(HTML) 3 Page - Texas Instruments

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ADS1146
ADS1147
ADS1148
www.ti.com
SBAS453C – JULY 2009 – REVISED APRIL 2010
THERMAL INFORMATION
ADS1146,
ADS1147,
ADS1148
THERMAL METRIC(1)
UNITS
PW
28
qJA
Junction-to-ambient thermal resistance(2)
79.5
qJC(top)
Junction-to-case(top) thermal resistance (3)
31.8
qJB
Junction-to-board thermal resistance (4)
40.9
°C/W
yJT
Junction-to-top characterization parameter (5)
3.0
yJB
Junction-to-board characterization parameter (6)
41.1
qJC(bottom)
Junction-to-case(bottom) thermal resistance (7)
n/a
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2)
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3)
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4)
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5)
The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6)
The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7)
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Copyright © 2009–2010, Texas Instruments Incorporated
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