74LVC1G175_3

© NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 03 — 21 May 2007

9 of 17

NXP Semiconductors

74LVC1G175

Single D-type flip-flop with reset; positive-edge trigger

12. Waveforms

Measurement points are given in Table 9.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig 7.

The clock input (CP) to output (Q) propagation delays, the clock pulse width, the D to CP set-up, the CP to

D hold times, and the maximum clock pulse frequency

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GND

GND

CP input

D input

Q output

Measurement points are given in Table 9.

Fig 8.

The master reset (MR) input to output (Q) propagation delays, the master reset pulse width, and the MR to

CP recovery time

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MR input

CP input

Q output

GND

GND