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74LVC2G240DP Arkusz danych(PDF) 8 Page - NXP Semiconductors |
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74LVC2G240DP Arkusz danych(HTML) 8 Page - NXP Semiconductors |
8 / 16 page 74LVC2G240_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 29 February 2008 8 of 16 NXP Semiconductors 74LVC2G240 Dual inverting buffer/line driver; 3-state 12. Waveforms Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 6. The data input (nA) to output (nY) propagation delays mna960 tPLH tPHL VM VM VM VM nY output nA input VI GND VOH VOL Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 7. 3-state enable and disable times mna961 tPLZ tPHZ outputs disabled outputs enabled VY VX outputs enabled output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH nOE input VOL VOH VCC VI VM GND GND tPZL tPZH VM VM Table 9. Measurement points Supply voltage Input Output VCC VM VM VX VY 1.65 V to 1.95 V 0.5 × VCC 0.5 × VCC VOL + 0.15 V VOH − 0.15 V 2.3 V to 2.7 V 0.5 × VCC 0.5 × VCC VOL + 0.15 V VOH − 0.15 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH − 0.3 V 3.0 V to 3.6 V 1.5 V 1.5 V VOL + 0.3 V VOH − 0.3 V 4.5 V to 5.5 V 0.5 × VCC 0.5 × V CC VOL + 0.3 V VOH − 0.3 V |
Podobny numer części - 74LVC2G240DP |
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Podobny opis - 74LVC2G240DP |
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