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74LVC2G126GN Arkusz danych(PDF) 3 Page - NXP Semiconductors |
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74LVC2G126GN Arkusz danych(HTML) 3 Page - NXP Semiconductors |
3 / 17 page 74LVC2G126_8 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 08 — 5 May 2008 3 of 17 NXP Semiconductors 74LVC2G126 Dual bus buffer/line driver; 3-state 6. Pinning information 6.1 Pinning 6.2 Pin description Fig 3. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) Fig 4. Pin configuration SOT833-1 (XSON8) 74LVC2G126 1OE VCC 1A 2OE 2Y 1Y GND 2A 001aab740 1 2 3 4 6 5 8 7 74LVC2G126 1Y 2OE VCC 2A 2Y 1A 1OE GND 001aab741 36 27 18 45 Transparent top view Fig 5. Pin configuration SOT996-2 (XSON8U) Fig 6. Pin configuration SOT902-1 (XQFN8U) 001aah949 74LVC2G126 Transparent top view 8 7 6 5 1 2 3 4 1OE 1A 2Y GND VCC 2OE 1Y 2A 001aaf056 1A 1Y 1OE 2Y 2OE 2A Transparent top view 3 6 1 5 7 2 terminal 1 index area 74LVC2G126 Table 3. Pin description Symbol Pin Description SOT505-2, SOT765-1, SOT833-1 and SOT996-2 SOT902-1 1OE 1 7 output enable input (active HIGH) 1A 2 6 data input 2Y 3 5 data output GND 4 4 ground (0 V) 2A 5 3 data input |
Podobny numer części - 74LVC2G126GN |
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Podobny opis - 74LVC2G126GN |
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