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ADC1113D125 Arkusz danych(PDF) 10 Page - NXP Semiconductors

Numer części ADC1113D125
Szczegółowy opis  Dual 11-bit ADC; serial JESD204A interface
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ADC1113D125_2
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 02 — 23 April 2010
10 of 41
NXP Semiconductors
ADC1113D125
ADC1113D125; serial JESD204A interface
11. Clock and digital output timing
[1]
Typical values measured at VDDA =3V, VDDD = 1.8 V, Tamb =25 °C. Minimum and maximum values are across the full temperature
range Tamb = −40 °C to +85 °C at VDDA =3 V, VDDD = 1.8 V; VI (INAP, INBP) − VI (INAM, INBM) = −1 dBFS; internal reference mode;
100 W differential applied to serial outputs; unless otherwise specified.
Table 7.
Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Clock timing input: pins CLKP and CLKM
fclk
clock frequency
100
-
125
Msps
tlat(data)
data latency time
-
14
-
clock cycle
δ
clk
clock duty cycle
DCS_EN = 1: en
30
50
70
%
DCS_EN = 0: dis
45
50
55
%
td(s)
sampling delay time
-
0.8
-
ns
twake
wake-up time
-
<tbd>
-
ns


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