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ADC1413D Arkusz danych(PDF) 11 Page - NXP Semiconductors |
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ADC1413D Arkusz danych(HTML) 11 Page - NXP Semiconductors |
11 / 43 page xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 11. Clock and digital output timing [1] Typical values measured at VDDA =3V, VDDD =1.8 V, Tamb =25 °C. Minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA =3V, VDDD = 1.8 V; VI (INAP, INBP) − VI (INAM, INBM) = −1 dBFS; internal reference mode; 100 W differential applied to serial outputs; unless otherwise specified. Table 7. Characteristics Symbol Parameter Conditions ADC1413D065 ADC1413D080 ADC1413D105 ADC1413D125 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max Clock timing input: pins CLKP and CLKM fclk clock frequency 20 - 65 60 - 80 75 - 105 100 - 125 Msps tlat(data) data latency time clock cycles 307 - 850 250 - 283 190 - 226 160 - 170 ns δ clk clock duty cycle DCS_EN = 1: en 30 50 70 30 50 70 30 50 70 30 50 70 % td(s) sampling delay time -0.8 -- 0.8 --0.8 --0.8 - ns twake wake-up time - <tbd> -- <tbd> -- <tbd> -- <tbd> -ns |
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