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DAC5311-Q1 Arkusz danych(PDF) 5 Page - Texas Instruments |
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DAC5311-Q1 Arkusz danych(HTML) 5 Page - Texas Instruments |
5 / 38 page PIN CONFIGURATION 1 2 3 6 5 4 SYNC SCLK D IN V OUT GND AV /V DD REF DAC5311-Q1 www.ti.com ...................................................................................................................................................................................................... SBAS470 – JUNE 2009 DCK PACKAGE SC70-6 (TOP VIEW) Table 1. PIN DESCRIPTION PIN NAME DESCRIPTION Level-triggered control input (active low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register and data are transferred in on the falling edges 1 SYNC of the following clocks. The DAC is updated following 16th clock cycle, unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC5311. See the SYNC Interrupt section for more details. 2 SCLK Serial clock input. Data can be transferred at rates up to 50 MHz. Serial data input. Data is clocked into the 16-bit input shift register on the falling edge of the serial clock 3 DIN input. 4 AVDD/VREF Power supply input, 1.8 V to 5.5 V. 5 GND Ground reference point for all circuitry on the part. 6 VOUT Analog output voltage from DAC. The output amplifier has rail-to-rail operation. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): DAC5311-Q1 |
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