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ADS8331IPWT Arkusz danych(PDF) 7 Page - Texas Instruments |
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ADS8331IPWT Arkusz danych(HTML) 7 Page - Texas Instruments |
7 / 40 page ADS8331 ADS8332 www.ti.com SBAS363 – DECEMBER 2009 TIMING CHARACTERISTICS: VA = 2.7V At TA = –40°C to +85°C, VA = 2.7V, and VBD = 1.65V, unless otherwise noted. (1) (2) PARAMETER MIN TYP MAX UNIT External, fCCLK = 1/2 fSCLK 0.5 10.5 MHz fCCLK Frequency, conversion clock, CCLK Internal 10.5 11 12.2 MHz tSU1 Setup time, rising edge of CS to EOC 1 CCLK tH1 Hold time, rising edge of CS to EOC 25 ns tWL1 Pulse duration, CONVST low 40 ns tWH1 Pulse duration, CS high 40 ns tSU2 Setup time, rising edge of CS to EOS 25 ns tH2 Hold time, rising edge of CS to EOS 25 ns tSU3 Setup time, falling edge of CS to first falling edge of SCLK 14 ns tWL2 Pulse duration, SCLK low 17 tSCLK – 17 ns tWH2 Pulse duration, SCLK high 12 tSCLK – 12 ns I/O clock only 40 ns I/O and conversion clocks 47.6 1000 ns tSCLK Cycle time, SCLK I/O clock, daisy-chain mode 40 ns I/O and conversion clocks, 47.6 1000 ns daisy-chain mode tD1 Delay time, falling edge of SCLK to SDO invalid 10pF load 8 ns tD2 Delay time, falling edge of SCLK to SDO valid 10pF load 35 ns tD3 Delay time, falling edge of CS to SDO valid, SDO MSB output 10pF load 35 ns tSU4 Setup time, SDI to falling edge of SCLK 8 ns tH3 Hold time, SDI to falling edge of SCLK 8 ns tD4 Delay time, rising edge of CS to SDO 3-state 10 ns tSU5 Setup time, last falling edge of SCLK before rising edge of CS 10 ns tD5 Delay time, falling edge of CS to deactivation of INT 40 ns tD6 Delay time, CDI to SDO in daisy-chain mode 10pF load 35 ns (1) All input signals are specified with tr = tf = 1.5ns (10% to 90% of VBD) and timed from a voltage level of (VIL + VIH)/2. (2) See the Timing Diagrams section. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): ADS8331 ADS8332 |
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