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ADXL346ACCZ Arkusz danych(PDF) 16 Page - Analog Devices

Numer części ADXL346ACCZ
Szczegółowy opis  3-Axis, 짹2 g/짹4 g/짹8 g/짹16 g Ultralow Power DIgital Accelerometer
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ADXL346
Rev. 0 | Page 16 of
40
Table 9. SPI Digital Input/Output
Limit1
Parameter
Test Conditions
Min
Max
Unit
Digital Input
Low Level Input Voltage (VIL)
0.3 × VDD I/O
V
High Level Input Voltage (VIH)
0.7 × VDD I/O
V
Low Level Input Current (IIL)
VIN = VDD I/O
0.1
μA
High Level Input Current (IIH)
VIN = 0 V
−0.1
μA
Digital Output
Low Level Output Voltage (VOL)
IOL = 10 mA
0.2 × VDD I/O
V
High Level Output Voltage (VOH)
IOH = −4 mA
0.8 × VDD I/O
V
Low Level Output Current (IOL)
VOL = VOL, max
10
mA
High Level Output Current (IOH)
VOH = VOH, min
−4
mA
Pin Capacitance
fIN = 1 MHz, VIN = 2.6 V
8
pF
1 Limits are based on characterization results; not production tested.
Table 10. SPI Timing (TA = 25°C, VS = 2.6 V, VDD I/O = 1.8 V)1
Limit2, 3
Parameter
Min
Max
Unit
Description
fSCLK
5
MHz
SPI clock frequency
tSCLK
200
ns
1/(SPI clock frequency) mark-space ratio for the SCLK input is 40/60 to 60/40
tDELAY
5
ns
CS falling edge to SCLK falling edge
tQUIET
5
ns
SCLK rising edge to CS rising edge
tDIS
10
ns
CS rising edge to SDO disabled
t
CS,DIS
150
ns
CS deassertion between SPI communications
tS
0.3 × tSCLK
ns
SCLK low pulse width (space)
tM
0.3 × tSCLK
ns
SCLK high pulse width (mark)
tSETUP
5
ns
SDI valid before SCLK rising edge
tHOLD
5
ns
SDI valid after SCLK rising edge
tSDO
40
ns
SCLK falling edge to SDO/SDIO output transition
tR4
20
ns
SDO/SDIO output low to output high transition
tF4
20
ns
SDO/SDIO output high to output low transition
1 The CS, SCLK, SDI, and SDO pins are not internally pulled up or down; they must be driven for proper operation.
2 Limits are based on characterization results; not production tested.
3 The timing values are measured corresponding to the input thresholds (VIL and VIH) given in Table 9.
4 Output rise and fall times are measured with a capacitive load of 150 pF.


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