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ADXRS450BRGZ Arkusz danych(PDF) 17 Page - Analog Devices

Numer części ADXRS450BRGZ
Szczegółowy opis  HIgh Performance, Digital Output Gyroscope
Download  28 Pages
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Strona internetowa  http://www.analog.com
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ADXRS450BRGZ Arkusz danych(HTML) 17 Page - Analog Devices

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Preliminary Technical Data
ADXRS450
Rev. PrA | Page 17 of 28
The fault conditions are initiated nearly simultaneously;
however, the timing for receiving fault codes when the CHK bit
is asserted is dependent upon the time required to generate
each unique fault. It takes no more than 50 ms for all of the
internal faults to be generated, and the fault register updated to
reflect the condition of the device. Until the CHK bit is cleared,
the status bits (ST[1:0]) are set to 0b10, indicating that the data
should be interpreted by the control module as self-test data.
After the CHK bit is deasserted, the fault conditions require an
additional 50 ms to decay, and the device to return to normal
operation. Refer to Figure 21 for the proper methodology for
asserting the check bit.
OV
The OV fault bit asserts if the internally regulated voltage
(nominally 3 V) is observed to exceed 3.3 V. This measurement
is low-pass filtered to prevent artifacts such as noise spikes from
asserting a fault condition. When an OV fault has occurred, the
PWR fault bit is asserted simultaneously. Because the OV fault
bit is not transmitted as part of a sensor data request, it is
recommended that the user read back the FAULT1 and FAULT0
memory registers upon the assertion of a PWR error. This
allows the user to determine the specific error condition.
UV
The UV fault bit asserts if the internally regulated voltage
(nominally 3 V) is observed to be less than 2.77 V. This
measurement is low-pass filtered to prevent artifacts such as
noise spikes from asserting a fault condition. When a UV fault
has occurred, the PWR fault bit is asserted simultaneously. As
the UV fault bit is not transmitted as part of a sensor data
request, it is recommended that the user read back the FAULT1
and FAULT0 memory registers upon the assertion of a PWR
error. This allows the user to determine the specific error
condition.
FAIL
The fail flag is asserted when a condition arises such that the
ST[0:1] bits are set to 0b00. This indicates that the device has
experienced a gross failure, and that the sensor data could
potentially be invalid.
AMP
The amp fault bit is asserted when the measured amplitude of
the silicon resonator has been significantly reduced. This
condition can occur if the voltage supplied to CP5 has fallen
below the requirements of the internal voltage regulator. This
fault bit is OR’ed with the CST fault such that during a sensor
data request, the CST bit position represents either an amp
failure or a CST failure. The full status register can then be read
from memory to validate the specific failure.
K-Bit Assertion: Recommended Start-Up Routine
The following diagram illustrates a recommended start-up
routine that can be implemented by the user. Alternate start-up
sequences can be employed; however, ensure that the response
from the ADXRS450 is handled correctly. If implemented
immediately after power is applied to the device, the total time
to implement the following fault detection routine is approx-
imately 200 ms. As described in the Device Data Latching
section, the data present in the device upon the assertion of the
CS signal is used in the next sequential command/response
exchange. This results in an apparent one transaction delay
before the data resulting from the assertion of the CHK
command is reported by the device. For all other read/write
interactions with the device, no such delay exists, and the MOSI
command is serviced during the next sequential command/
response exchange. Note that when the CHK bit is deasserted, if
the user tries to obtain data from the device before the CST
fault flag has cleared, the device reports the data as error data.


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