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ADXRS450BEYZ-RL Arkusz danych(PDF) 16 Page - Analog Devices |
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ADXRS450BEYZ-RL Arkusz danych(HTML) 16 Page - Analog Devices |
16 / 28 page ADXRS450 Preliminary Technical Data Rev. PrA | Page 16 of 28 or sensor data request can be issued after a sequential transfer delay of only 10 μs is observed. Regardless of the commands that are subsequently issued to the device, once a write procedure has been initiated, the operation proceeds through to completion (requiring 17 ms). Fault Register Bit Definitions This section describes the bits available for signaling faults to the user. The individual bits of the fault register are updated asynchronously depending on their respective detection criteria; however, it is recommended that the fault register is read at a rate of at least 250 Hz. When asserted, the individual status bit does not deassert until it is read by the master device. If the error persists after a fault register read, the status bit immediately reasserts, and remains asserted until the next sequential command/response exchange. The full fault register is appended to every sensor data request. It can also be accessed by issuing a read command to Register 0x0A. Table 13. Quick Guide—Fault Register Bit Definitions Bit Name Description PLL PLL failure Q Quadrature error NVM NVM memory fault POR Power-on reset failed to initialize UV Regulator under voltage Amp Amplitude detection failure PWR Power regulation failed: overvoltage/undervoltage CST Continuous self-test failure CHK Check: generate faults OV Regulator overvoltage Fail Failure which sets the ST[1:0] bits to 0b00 PLL PLL is the bit indicating that the device has had a failure in the phase locked-loop functional circuit block. This occurs when the PLL has failed to achieve sync with the resonator structure. If the PLL status flag is active, the ST bits of the sensor data response set to 0b00, indicating that the response contains potentially invalid rate data. Q A Q fault can be asserted based on two independent quadrature calculations. Located in the quad memory (Register 0x08) is a value corresponding to the total instantaneous quadrature present in the device. If this value exceeds 4096 LSB, a Q fault is issued. Because quadrature build-up can contribute to an offset error, the ADXRS450 has integrated methods for dynamically cancelling the effects of quadrature. An internal quadrature accumulator records the amount of quadrature correction performed by the ADXRS450. Excessive quadrature is associated with offset errors. A Q fault is issued once the quadrature error present in the device has contributed to an equivalent of 4°/sec (typical) of rate offset. NVM An NVM error transmits to the control module when the internal NVM data fails a checksum calculation. This check is performed once every 50 μs, and does not include the DNC0 or PID memory registers. POR An internal check is performed on device startup to ensure that the volatile memory of the device is functional. This is accom- plished by programming a known value from the device ROM into a volatile memory register. This value is then continuously compared to the known value in ROM every 1 μs for the duration of the device’s operation. If the value stored in the volatile memory changes, or does not match the value stored in ROM, the POR error flag is asserted. The value stored in ROM is rewritten to the volatile memory upon a device power cycle. PWR The device performs a continuous check of the internal 3 V regulated voltage level. If either an overvoltage (OV) or under- voltage (UV) fault is asserted, then the PWR bit is also asserted. This condition occurs if the regulated voltage is observed to be either above 3.3 V or below 2.77 V. An internal low-pass filter removes high frequency glitching effects to prevent the PWR bit from asserting unnecessarily. To determine if the fault is a result of an overvoltage or undervoltage condition, the OV and UV fault bits must be analyzed. CST The ADXRS450 is designed with continuous self-test functionality. Measured self-test amplitudes are compared against the limits presented in Table 1. Deviations from this value result in reported self-test errors. There are two thresholds for a self-test failure. • Self-test value > ±512 LSB from nominal results in an assertion of the self-test flag in the fault register • Self-test value > ±1856 LSB from nominal results in both an assertion of the self-test flag in the fault register as well as setting the ST[1:0] bits to 0b00, indicating that the rate data contained in the sensor data response is potentially invalid. CHK The CHK bit is transmitted by the control module to the ADXRS450 as a method of generating faults. By asserting the CHK bit, the device creates conditions that result in the generation of all faults represented through the fault register. For example, the self-test amplitude is deliberately altered to exceed the fault detection threshold, resulting in a self test error. In this way, the device is capable of checking both its ability to detect a fault condition, as well as its ability to report that fault to the control module. |
Podobny numer części - ADXRS450BEYZ-RL |
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Podobny opis - ADXRS450BEYZ-RL |
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