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Si5326 Arkusz danych(PDF) 1 Page - Silicon Laboratories |
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Si5326 Arkusz danych(HTML) 1 Page - Silicon Laboratories |
1 / 50 page Preliminary Rev. 0.15 4/10 Copyright © 2010 by Silicon Laboratories Si5317 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Si5317 P IN-C ONTROLLED 1–710 M H Z J ITTER C LEANING C LOCK Features Applications Description The Si5317 is a flexible 1:1 jitter cleaning clock for high-performance applications that require jitter attenuation without clock multiplication. The Si5317 accepts a single clock input ranging from 1 to 710 MHz and generates two low jitter clock outputs at the same frequency. The clock frequency range and loop bandwidth are selectable from a simple look-up table. The Si5317 is based on Silicon Laboratories' 3rd-generation DSPLL® technology, which provides jitter attenuation on any frequency in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is user selectable, providing jitter performance optimization at the application level. Functional Block Diagram Provides jitter attenuation on any frequency One clock input / two clock outputs Input/output frequency range: 1–710 MHz Ultra low jitter: 300 fs (12 kHz–20 MHz) typical Simple pin control interface Selectable loop bandwidth for jitter attenuation: 60 Hz–8.4 kHz Selectable output clock signal format: LVPECL, LVDS, CML or CMOS Single supply: 1.8, 2.5, or 3.3 V VCO freeze during LOS/LOL Loss of lock and loss of signal alarms On-chip voltage regulator with high PSRR Small size: 6 x 6 mm, 36-QFN Wide temperature range: –40 to +85 ºC Data converter clocking Wireless infrastructure Networking, SONET/SDH Switches and routers Medical instrumentation Test and measurement DSPLL ® Clock In Clock Out1 Signal Format [1:0] Status/Control Loss of Lock Loss of Signal Bandwidth Select [1:0] XTAL/Clock Rate [1:0] Frequency Table High PSRR Regulator Frequency Select [3:0] Clock Out2 XTAL/Clock Phase Skew INC/DEC VDD (1.8, 2.5, 3.3 V) GND Ordering Information: See page 43. Pin Assignments 1 2 3 29 30 31 32 33 34 35 36 20 21 22 23 24 25 26 27 10 11 12 13 14 15 16 17 4 5 6 7 8 FRQTBL NC RST NC LOS GND VDD XA NC BWSEL0 BWSEL1 FRQSEL1 FRQSEL2 FRQSEL3 GND Pad FRQSEL0 DEC 9 18 19 28 XB INC P RELIMINARY D ATA S HEET |
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