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ADS8201IBRGET Arkusz danych(PDF) 11 Page - Texas Instruments

Numer części ADS8201IBRGET
Szczegółowy opis  2.2V to 5.5V,Low-Power, 12-Bit, 100kSPS, 8-Channel Data Acquisition System with PGA and SPI??Interface
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ADS8201IBRGET Arkusz danych(HTML) 11 Page - Texas Instruments

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ADS8201
www.ti.com
SLAS534B – JULY 2009 – REVISED MAY 2010
REFERENCE
The ADS8201 requires an external reference. A clean, low-noise, well-decoupled supply voltage on this pin is
required to ensure good converter performance. A low-noise bandgap reference such as the REF3240 can be
used to drive this pin. A 10mF ceramic decoupling capacitor is required between the REF and REFGND pins of
the converter. These capacitors should be placed as close as possible to the respective device pins. The
REFGND pin should be connected by its own via to the analog ground plane of the printed circuit board (PCB)
with the shortest possible trace. The minimum reference supported by the ADS8201 is 2.048V.
CONVERTER OPERATION
The ADS8201 has an internal clock that controls the conversion rate; the frequency of this clock is 4MHz,
however, this clock can have a variance of up to 20%. The Conversion Delay System Configuration Register
(SCR) at address 0Ah can be used to offset the conversion clock variance. This register allows the conversion
delay to be programmed after conversion from a range of 0.5ms to 15ms. The default conversion delay is set to
4.5ms; however, the appropriate conversion delay can be selected to achieve maximum throughput. Unless the
device is in power-down mode, the internal clock is always on. The minimum acquisition time is 8.5 clock cycles
(this period is equivalent to 2.125ms at 4MHz) after CONVST is asserted. It takes 13.5 conversion clocks
(CCLKs), or approximately 3.375ms, to complete one conversion. The data can be clocked out during the next
4.5ms through the serial interface. Care must be taken to ensure that the next conversion is not initiated until
10ms after the first convert start is asserted.
ADC OPERATING MODE SUMMARY
Table 2 summarizes the ADC operating modes for the ADS8201.
Table 2. ADC Operating Modes
ADC
OPERATING
ADC
CHANNEL
MODE
TRIGGER
CONTROL
DELAY MUX
MULTI-SCAN
AUTO PD
MODE DESCRIPTION
Idle
0 (000)
N/A
N/A
N/A
N/A
ADC idle
(no trigger)
1 (001b)
Reserved
Manual
2 (010b)
Manual
Off
N/A
Off
Manual trigger with manual-channel
trigger
Manual
Manual trigger with manual-channel and
3 (011b)
Manual
On
N/A
Off
trigger
delay mux
4 (100b)
Auto trigger
Manual
On
N/A
Off
Auto trigger with manual-channel
Auto
Auto trigger with auto-channel and
5 (101b)
Auto trigger
N/A
Single scan
Off
increment
single-scan
Auto
Auto trigger with auto-channel and
6 (110b)
Auto trigger
N/A
Multi-scan
Off
increment
multi-scan
7 (111b)
Reserved
Copyright © 2009–2010, Texas Instruments Incorporated
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