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SN74AUP1T86DCKR Arkusz danych(PDF) 2 Page - Texas Instruments |
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SN74AUP1T86DCKR Arkusz danych(HTML) 2 Page - Texas Instruments |
2 / 11 page = 2k 2k + 1 LOGIC-IDENTITY ELEMENT EVEN-PARITY ELEMENT ODD-PARITY ELEMENT The output is active (low) if all inputs stand at the same logic level (i.e., A = B). The output is active (low) if an even number of inputs (i.e., 0 or 2) are active. The output is active (high) if an odd number of inputs (i.e., only 1 of the 2) are active. = 1 EXCLUSIVE OR SN74AUP1T86 SCES805 – APRIL 2010 www.ti.com ORDERING INFORMATION(1) TA PACKAGE(2) ORDERABLE PART NUMBER TOP-SIDE MARKING(3) Reel of 3000 SN74AUP1T86DCKR –40°C to 85°C SOT (SC-70) – DCK 6H_ Reel of 250 SN74AUP1T86DCKT (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. (2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. (3) The actual top-side marking has one additional character that designates the wafer fab/assembly site. FUNCTION TABLE INPUTS OUTPUT (Lower Level Input) (VCC CMOS) A B Y L L L L H H H L H H H L Supply VCC = 2.3 V to 2.7 V (2.5 V) INPUTS OUTPUT VT+ max = VIH min CMOS VT- min = VIL max A B Y VIH = 1.1 V VOH = 1.85 V VIL = 0.35 V VOL = 0.45 V Supply VCC = 3 V to 3.6 V (3.3 V) INPUTS OUTPUT VT+ max = VIH min CMOS VT- min = VIL max A B Y VIH = 1.19 V VOH = 2.55 V VIL = 0.5 V VOL = 0.45 V LOGIC DIAGRAM (XOR GATE) 2 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN74AUP1T86 |
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