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TMP320C6713PYPM20EP Arkusz danych(PDF) 6 Page - Texas Instruments |
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TMP320C6713PYPM20EP Arkusz danych(HTML) 6 Page - Texas Instruments |
6 / 131 page SM320C6713-EP SM320C6713B-EP SGUS049I – AUGUST 2003 – REVISED SEPTEMBER 2009 www.ti.com List of Tables 3-1 Terminal Assignments for 272-Ball GDP Package (in Order of Ball No.) ................................................ 12 3-2 Characteristics of the C6713 and C6713B Processor ....................................................................... 16 4-1 320C6713/13B Memory Map Summary ...................................................................................... 20 4-2 EMIF Registers ................................................................................................................... 22 4-3 L2 Cache Registers .............................................................................................................. 23 4-4 Interrupt Selector Registers ..................................................................................................... 23 4-5 Device Registers ................................................................................................................. 24 4-6 EDMA Parameter RAM ......................................................................................................... 24 4-7 EDMA Registers .................................................................................................................. 25 4-8 Quick DMA (QDMA) and Pseudo Registers ................................................................................. 25 4-9 PLL Controller Registers ........................................................................................................ 25 4-10 McASP0 and McASP1 Registers .............................................................................................. 26 4-11 I2C0 and I2C1 Registers ........................................................................................................ 28 4-12 HPI Registers ..................................................................................................................... 28 4-13 Timer 0 and Timer 1 Registers ................................................................................................. 28 4-14 McBSP0 and McBSP1 Registers .............................................................................................. 29 4-15 GPIO Registers ................................................................................................................... 29 5-1 Device Configurations Pins at Device Reset (HD[4:3], HD8, HD12 [13B only], and CLKMODE0) ................... 35 5-2 HPI_EN (HD14 Pin) Peripheral Selection (HPI or McASP1, and Select GPIO Pins) .................................. 36 5-3 Device Configuration Register (DEVCFG) [Address Location: 0x019C0200 −0x019C02FF] .......................... 36 5-4 Device Configuration Register (DEVCFG) Selection Bit Descriptions .................................................... 37 5-5 Peripheral Pin Selection Matrix ................................................................................................ 38 5-6 C6713/13B Device Multiplexed/Shared Pins ................................................................................. 38 6-1 320C6713 and C6713B Device Part Numbers (P/Ns) and Ordering Information ....................................... 56 7-1 CPU CSR Bit Field Description ................................................................................................ 59 7-2 CCFG Register Bit Field Description .......................................................................................... 60 7-3 DSP Interrupts .................................................................................................................... 60 7-4 Interrupt Selector ................................................................................................................. 62 7-5 External Interrupt Sources and Peripheral Module Control ................................................................. 63 7-6 EDMA Channels .................................................................................................................. 64 7-7 EDMA Selector ................................................................................................................... 65 7-8 EDMA Event Selector Registers (ESEL0 Register (0x01A0 FF00) ....................................................... 66 7-9 EDMA Event Selector Registers—ESEL1 Register (0x01A0 FF04) ...................................................... 66 7-10 EDMA Event Selector Registers—ESEL3 Register (0x01A0 FF0C) ..................................................... 66 7-11 EDMA Event Selection Registers (ESEL0, ESEL1, and ESEL3) Description ............................................ 66 8-1 PLL Lock and Reset Times ..................................................................................................... 68 8-2 CLKOUT Signals, Default Settings, and Control ............................................................................. 68 8-3 PLL Clock Frequency Ranges ................................................................................................. 69 8-4 PLL Control/Status Register (PLLCSR) (0x01B7 C100) ................................................................... 70 8-5 PLL Control/Status Register (PLLCSR) Description ......................................................................... 70 8-6 PLL Multiplier (PLLM) Control Register (0x01B7 C110) .................................................................... 70 8-7 PLL Multiplier (PLLM) Control Register Description ......................................................................... 71 8-8 PLL Wrapper Divider x Registers (PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3) (0x01B7 C114, 0x01B7 C118, 0x01B7 C11C, and 0x01B7 C120, respectively) ....................................... 71 8-9 PLL Wrapper Divider x Registers (Prescaler Divider D0 and Post-Scaler Dividers D1, D2, and D3) Description .......................................... 71 8-10 Oscillator Divider 1 (OSCDIV1) Register (0x01B7 C124) .................................................................. 72 6 List of Tables Copyright © 2003–2009, Texas Instruments Incorporated |
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