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ADS62P15 Arkusz danych(PDF) 8 Page - Texas Instruments |
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ADS62P15 Arkusz danych(HTML) 8 Page - Texas Instruments |
8 / 64 page DIGITAL CHARACTERISTICS ADS62P15 SLAS572B – OCTOBER 2007 – REVISED APRIL 2009 .................................................................................................................................................... www.ti.com The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1. AVDD=3.3V, DRVDD=1.8V to 3.3V, unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS High-level input voltage 2.4 V Low-level input voltage 0.8 V High-level input current 33 µA Low-level input current –33 µA Input capacitance 4 Pf DIGITAL OUTPUTS – CMOS MODE, DRVDD = 1.8 to 3.3V High-level output voltage DRVDD V Low-level output voltage 0 V Output capacitance (internal to device) 2 pF DIGITAL OUTPUTS – LVDS MODE(1) (2), DRVDD = 3.3V High-level output voltage 1375 mV Low-level output voltage 1025 mV |VOD| Output differential voltage 250 350 500 mV VOS Output offset voltage Common-mode voltage of OUTP and OUTM 1200 mV Output capacitance inside the device, from Output Capacitance 2 pF either output to ground (1) LVDS buffer current setting, IO = 3.5 mA. (2) External differential load resistance between the LVDS output pairs, RLOAD = 100 Ω. 8 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS62P15 |
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