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SN74AUP1G32DBVTE4 Arkusz danych(PDF) 2 Page - Texas Instruments

Numer części SN74AUP1G32DBVTE4
Szczegółowy opis  LOW-POWER SINGLE 2-INPUT POSITIVE-OR GATE
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Producent  TI [Texas Instruments]
Strona internetowa  http://www.ti.com
Logo TI - Texas Instruments

SN74AUP1G32DBVTE4 Arkusz danych(HTML) 2 Page - Texas Instruments

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AUP
LVC
AUP
AUP
LVC
Static-Power Consumption
(
µA)
Dynamic-Power Consumption
(pF)
Single, dual, and triple gates
3.3-V
Logic
3.3-V
Logic
0%
20%
40%
60%
80%
100%
0%
20%
40%
60%
80%
100%
−0.5
0
0.5
1
1.5
2
2.5
3
3.5
0
5
10
15
20
25
30
35
40
45
Time − ns
AUP1G08 data at CL = 15 pF
Output
Input
Switching Characteristics
at 25 MHz
1
2
4
A
B
Y
SN74AUP1G32
SCES580F – JUNE 2004 – REVISED MARCH 2010
www.ti.com
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
Figure 1. AUP–The Lowest-Power Family
Figure 2. Excellent Signal Integrity
ORDERING INFORMATION(1)
TA
PACKAGE(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING(3)
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YFP
Reel of 3000
SN74AUP1G32YFPR
_ _ _HG_
(Pb-free)
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP
Reel of 3000
SN74AUP1G32YZPR
_ _ _HG_
(Pb-free)
QFN – DRY
Reel of 5000
SN74AUP1G32DRYR
HG
–40°C to 85°C
uQFN – DSF
Reel of 5000
SN74AUP1G32DSFR
HG
Reel of 3000
SN74AUP1G32DBVR
SOT (SOT-23) – DBV
H32_
Reel of 250
SN74AUP1G32DBVT
Reel of 3000
SN74AUP1G32DCKR
SOT (SC-70) – DCK
HG_
Reel of 250
SN74AUP1G32DCKT
SOT (SOT-553) – DRL
Reel of 4000
SN74AUP1G32DRLR
HG_
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2)
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3)
DBV/DCK/DRL: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
YFP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
FUNCTION TABLE
INPUTS
OUTPUT
Y
A
B
L
L
L
L
H
H
H
L
H
H
H
H
LOGIC DIAGRAM (POSITIVE LOGIC)
2
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Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): SN74AUP1G32


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