ADP3193A

Rev. 1 | Page 6 of 29 | www.onsemi.com

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

1

EN

2

PWRGD

3

FBRTN

4

FB

5

COMP

6

SS

7

DELAY

8

ILIMIT

24 VID7

23 VCC

22 PWM1

21 PWM2

20 PWM3

19 SW1

18 SW2

17 SW3

ADP3193A

TOP VIEW

(Not to Scale)

NOTES

1. THE EXPOSED EPAD ON BOTTOM SIDE OF PACKAGE IS AN

ELECTRICAL CONNECTION AND SHOULD BE SOLDERED TO GROUND.

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

EN

Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low.

2

PWRGD

Power-Good Output. Open-drain output that signals when the output voltage is outside of the proper operating range.

3

FBRTN

Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage.

4

FB

Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor between this pin

and the output voltage sets the no load offset point.

5

COMP

Error Amplifier Output and Compensation Point.

6

SS

Soft Start Delay Setting Input. An external capacitor connected between this pin and GND sets the soft start ramp-up time.

7

DELAY

Delay Timer Setting Input. An external capacitor connected between this pin and GND sets the overcurrent latch-off

delay time, boot voltage hold time, EN delay time, and PWRGD delay time.

8

ILIMIT

Current-Limit Set Point. An external resistor from this pin to GND sets the current-limit threshold of the converter.

9

RT

Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator

frequency of the device.

10

RAMPADJ

PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal PWM ramp.

11

CSREF

Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense amplifier

and the power-good and crowbar functions. This pin should be connected to the common point of the output inductors.

12

CSSUM

Current Sense Summing Node. External resistors from each switch node to this pin sum the average inductor currents

to measure the total output current.

13

CSCOMP

Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determines the gain of the

current sense amplifier and the positioning loop response time.

14

GND

Ground. All internal biasing and the logic output signals of the device are referenced to this ground.

15

OD

Output Disable Logic Output. This pin is actively pulled low when the EN input is low or when VCC is below its UVLO

threshold to signal to the driver IC that the driver high-side and low-side outputs should go low.

16

IREF

17 to 19

SW3 to SW1

Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases should be

left open.

20 to 22

PWM3 to PWM1

Connecting PWM3 output to VCC causes that phase to turn off, allowing the ADP3193A to operate as a 2- or 3-phase

controller.

23

VCC

Supply Voltage. A 340 Ω resistor should be placed between the 12 V system supply and the VCC pin. The internal

shunt regulator maintains VCC = 5 V.

24 to 31

VID7 to VID0

Voltage Identification DAC Inputs. These eight pins are pulled down to GND, providing a logic zero if left open. When

in normal operation mode, the DAC output programs the FB regulation voltage from 0.5 V to 1.6 V (see

32

VIDSEL

VID DAC Selection Pin. The logic state of this pin determines whether the internal VID DAC decodes VID0 to VID7 as

extended VR10 or VR11 inputs.