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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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ADP3212A Arkusz danych(PDF) 5 Page - ON Semiconductor |
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ADP3212A Arkusz danych(HTML) 5 Page - ON Semiconductor |
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5 / 35 page  ADP3212A, NCP3218A http://onsemi.com 5 ELECTRICAL CHARACTERISTICS VCC = PVCC = 5.0 V, FBRTN = PGND = GND = 0 V, H = 5.0 V, L = 0 V, EN = VARFREQ = H, DPRSLP = L, PSI = 1.05 V, VVID = VDAC = 1.2000 V, TA = −40°C to 100°C, unless otherwise noted. (Note 1) Current entering a pin (sink current) has a positive sign. Parameter Symbol Conditions Min Typ Max Units VOLTAGE CONTROL − VOLTAGE ERROR AMPLIFIER (VEAMP) FB, LLINE Voltage Range (Note 2) VFB, VLLINE Relative to CSREF = VDAC −200 +200 mV FB, LLINE Offset Voltage (Note 2) VOSVEA Relative to CSREF = VDAC −0.5 +0.5 mV LLINE Bias Current ILLINE −100 +100 nA FB Bias Current IFB −1.0 +1.0 mA LLINE Positioning Accuracy VFB − VVID Measured on FB relative to VVID, LLINE forced 80 mV below CSREF −77.5 −80 −82.5 mV COMP Voltage Range (Note 2) VCOMP 0.85 4.0 V COMP Current ICOMP COMP = 2.0 V, CSREF = VDAC FB forced 200 mV below CSREF FB forced 200 mV above CSREF −0.75 6.0 mA COMP Slew Rate SRCOMP CCOMP = 10 pF, CSREF = VDAC, Open loop configuration FB forced 200 mV below CSREF FB forced 200 mV above CSREF 15 −20 V/ms Gain Bandwidth (Note 2) GBW Non−inverting unit gain configuration, RFB = 1 kW 20 MHz VID DAC VOLTAGE REFERENCE VDAC Voltage Range (Note 2) See VID table 0 1.5 V VDAC Accuracy VFB − VVID Measured on FB (includes offset), relative to VVID VVID = 0.5000 V to 1.5000 V, T = −10°C to 100°C VVID = 0.5000 V to 1.5000 V, T = −40°C to 100°C VVID = 0.3000 V to 0.4875 V, T = −10°C to 100°C VVID = 0.3000 V to 0.4875 V, T = −40°C to 100°C −7.5 −9.0 −9.0 −10 +7.5 +9.0 +9.0 +10 mV VDAC Differential Non−linearity (Note 2) −1.0 +1.0 LSB VDAC Line Regulation ΔVFB VCC = 4.75 V to 5.25 V 0.001 % VDAC Boot Voltage VBOOTFB Measured during boot delay period 1.100 V Soft−Start Delay (Note 2) tDSS Measured from EN pos edge to FB = 50 mV 200 ms Soft−Start Time tSS Measured from FB = 50 mV to FB settles to 1.1 V within 5% 1.4 ms Boot Delay tBOOT Measured from FB settling to 1.1 V within 5% to CLKEN neg edge 60 ms VDAC Slew Rate (Note 2) Soft−Start Non−LSB VID step, DPRSLP = H, Slow C4 Entry/Exit Non−LSB VID step, DPRSLP = L, Fast C4 Exit LSB VID step, DVID transition GPU Mode, Non−LSB VID step, Fast Entry/Exit 0.0625 0.25 1.0 0.4 1.0 LSB/ ms FBRTN Current IFBRTN −90 −200 mA VOLTAGE MONITORING and PROTECTION − POWER GOOD CSREF Undervoltage Threshold VUVCSREF Relative to nominal VDAC voltage −240 −300 −360 mV CSREF Overvoltage Threshold VOVCSREF Relative to nominal VDAC voltage, T = −10°C to 100°C T = −40°C to 100°C 150 140 200 200 250 250 mV 1. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). 2. Guaranteed by design or bench characterization, not production tested. 3. Based on bench characterization data. 4. Timing is referenced to the 90% and 10% points, unless otherwise noted. |
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Podobny opis - ADP3212A |
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