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ADT7463ARQ Arkusz danych(PDF) 10 Page - ON Semiconductor |
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ADT7463ARQ Arkusz danych(HTML) 10 Page - ON Semiconductor |
10 / 52 page REV. C –10– ADT7463 R/W 0 SCL SDA 10 1 1 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY ADT7463 START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE FRAME 2 ADDRESS POINTER REGISTER BYTE 19 1 ACK. BY ADT7463 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY ADT7463 STOP BY MASTER FRAME 3 DATA BYTE 1 9 SCL (CONTINUED) SDA (CONTINUED) Figure 7. Writing a Register Address to the Address Pointer Register, Then Writing Data to the Selected Register 2. Data is sent over the serial bus in sequences of nine clock pulses, eight bits of data followed by an Acknowledge Bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low-to-high transition when the clock is high may be interpreted as a STOP signal. The number of data bytes that can be transmitted over the serial bus in a single READ or WRITE operation is limited only by what the master and slave devices can handle. 3. When all data bytes have been read or written, stop conditions are established. In WRITE mode, the master pulls the data line high during the tenth clock pulse to assert a STOP condition. In READ mode, the master device overrides the acknowledge bit by pulling the data line high during the low period before the ninth clock pulse. This is known as No Acknowledge. The master then takes the data line low during the low pe- riod before the 10th clock pulse, and then high during the 10th clock pulse to assert a STOP condition. Any number of bytes of data can be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation. In the case of the ADT7463, write operations contain either one or two bytes, and read operations contain one byte and perform the following functions. To write data to one of the device data registers or read data from it, the address pointer register must be set so that the correct data register is addressed, then data can be written into that register or read from it. The first byte of a write operation always contains an address that is stored in the address pointer register. If data is to be written to the device, then the write operation contains a second data byte that is written to the register selected by the address pointer register. This is illustrated in Figure 7. The device address is sent over the bus followed by R/W being set to 0. This is followed by two data bytes. The first data byte is the address of the internal data register to be written to, which is stored in the address pointer register. The second data byte is the data to be written to the internal data register. Rev. 4 | Page 10 of 52 | www.onsemi.com |
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