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ADT7473ARQZ Arkusz danych(PDF) 11 Page - ON Semiconductor |
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ADT7473ARQZ Arkusz danych(HTML) 11 Page - ON Semiconductor |
11 / 74 page ADT7473 http://onsemi.com 11 R/W 0 SCL SDA 10 1 1 1 0 D7 D6 D5 D4 D3 D2 D1 D0 STOP BY MASTER START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE FRAME 2 ADDRESS POINTER REGISTER BYTE 1 1 9 ACK. BY ADT7473/ADT7473−1 9 ACK. BY ADT7473/ADT7473−1 Figure 18. Writing to the Address Pointer Register Only Figure 19. Reading Data from a Previously Selected Register R/W 0 SCL SDA 10 1 1 1 0 D7 D6 D5 D4 D3 D2 D1 D0 NO ACK. BY MASTER STOP BY MASTER START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE FRAME 2 DATA BYTE FROM ADT7473 1 1 9 ACK. BY ADT7473/ADT7473−1 9 It is possible to read a data byte from a data register without first writing to the address pointer register, if the address pointer register is already at the correct value. However, it is not possible to write data to a register without writing to the address pointer register, because the first data byte of a write is always written to the address pointer register. In addition to supporting the send byte and receive byte protocols, the ADT7473/ADT7473−1 also supports the read byte protocol. (See System Management Bus (SMBus) Specifications Version 2 for more information; this document is available from Intel.) If several read or write operations must be performed in succession, the master can send a repeat start condition instead of a stop condition to begin a new operation. Write Operations The SMBus specification defines several protocols for various read and write operations. The ADT7473/ ADT7473−1 uses the following SMBus write protocols. The following abbreviations are used in the diagrams: S—Start P—Stop R—Read W—Write A—Acknowledge A—No Acknowledge Send Byte In this operation, the master device sends a single command byte to a slave device, as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7−bit slave address followed by the write bit (active low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends a command code. 5. The slave asserts ACK on SDA. 6. The master asserts a stop condition on SDA and the transaction ends. For the ADT7473/ADT7473−1, the send byte protocol is used to write a register address to RAM for a subsequent single−byte read from the same address. This operation is illustrated in Figure 20. Figure 20. Setting a Register Address for Subsequent Read SLAVE ADDRESS WA SA P REGISTER ADDRESS 23 15 6 4 If the master is required to read data from the register immediately after setting up the address, it can assert a repeat start condition immediately after the final ACK and carry out a single−byte read without asserting an intermediate stop condition. Write Byte In this operation, the master device sends a command byte and one data byte to the slave device, as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7−bit slave address followed by the write bit (active low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends a command code. 5. The slave asserts ACK on SDA. 6. The master sends a data byte. 7. The slave asserts ACK on SDA. 8. The master asserts a stop condition on SDA, and the transaction ends. The single byte write operation is illustrated in Figure 21. Figure 21. Single−Byte Write to a Register SLAVE ADDRESS W A DATA SA A P REGISTER ADDRESS 23 15 6 7 8 4 |
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