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CAT28C17APA-20T Arkusz danych(PDF) 8 Page - ON Semiconductor |
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CAT28C17APA-20T Arkusz danych(HTML) 8 Page - ON Semiconductor |
8 / 12 page CAT28C17A http://onsemi.com 8 Figure 7. DATA Polling ADDRESS I/O7 WE OE CE DIN = X DOUT = X DOUT = X tOEH tOE tWC tOES Hardware Data Protection The following is a list of hardware data protection features that are incorporated into the CAT28C17A. 1. VCC sense provides for write protection when VCC falls below 3.0 V min. 2. A power on delay mechanism, tINIT (see AC characteristics), provides a 5 to 20 ms delay before a write sequence, after VCC has reached 3.0 V min. 3. Write inhibit is activated by holding any one of OE low, CE high or WE high. 4. Noise pulses of less than 20 ns on the WE or CE inputs will not result in a write cycle. |
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