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CAT1232LP Arkusz danych(PDF) 3 Page - ON Semiconductor |
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CAT1232LP Arkusz danych(HTML) 3 Page - ON Semiconductor |
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3 / 12 page  CAT1232LP, CAT1832 © 2009 SCILLC. All rights reserved. 3 Doc. No. MD-3018 Rev. F Characteristics subject to change without notice ELECTRICAL CHARACTERISTICS Unless otherwise stated, 1.0 V - VCC - 5.5 V and over the operating temperature range of -40ºC to +85ºC. All voltages are referenced to ground. Symbol Parameter Conditions Min Typ Max Units VCC Supply Voltage 1.0 5.5 V VCC = 5.5 V, CAT1232LP 35 50 ICC1 Supply Current VCC = 3.6 V, CAT1832 20 35 µA (5) 2 VIH ST and PBRST ¯¯¯¯¯¯ Input High Level (6) VCC - 0.4 V VCC + 0.3 V V VCC = 5.5 V, CAT1232LP -0.3 0.8 VIL ST and PBRST ¯¯¯¯¯¯ Input Low Level VCC = 3.6 V, CAT1832 0.5 V VCCTP VCC Trip Point (TOL = GND) CAT1232LP 4.50 4.62 4.74 V VCCTP VCC Trip Point (TOL = VCC) CAT1232LP 4.25 4.37 4.49 V VCCTP VCC Trip Point (TOL = GND) CAT1832 2.80 2.88 2.97 V VCCTP VCC Trip Point (TOL = VCC) CAT1832 2.47 2.55 2.64 V tTD Watchdog Time-Out Period TD = GND 62.5 150 250 ms tTD Watchdog Time-Out Period TD = VCC 500 1200 2000 ms tTD Watchdog Time-Out Period TD floating 250 600 1000 ms VOH Output Voltage I = -500 µA (3) VCC -0.5 V VCC -0.1 V V IOH Output Current Output = 2.4 V (2) -350 µA IOL Output Current Output = 0.4 V 10 mA IIL Input Leakage (1) -1.0 1.0 µA RPU Internal Pull-Up Resistor (1) 32 40 55 kΩ CIN Input Capacitance 5 pF COUT Output Capacitance 7 pF tPB PBRST ¯¯¯¯¯¯ Manual Reset Minimum Low Time PBRST ¯¯¯¯¯¯ = VIL 20 ms tRST Reset Active Time 250 600 1000 ms tST ST ¯¯ Pulse Width (4) 20 ns tRPD VCC Fail Detect to RESET or RESET ¯¯¯¯¯¯ 5 8 µs tF VCC Slew Rate 20 µs tPDLY PBRST ¯¯¯¯¯¯ Stable LOW to RESET and RESET ¯¯¯¯¯¯ Active 20 ms tRPU VCC Detect to RESET or RESET ¯¯¯¯¯¯ Inactive tRISE = 5 µs 250 600 1000 ms tR VCC Slew Rate 4.25 V to 4.75 V 0 ns Notes: (1) PBRST ¯¯¯¯¯¯ is internally pulled HIGH to V CC through a nominal 40 kΩ resistor (RPU). (2) RESET ¯¯¯¯¯¯ is an open drain output on the CAT1232LP. (3) RESET remains within 0.5 V of VCC on power-down until VCC falls below 2 V. RESET remains within 0.5 V of ground on power-down until VCC falls below 2.0 V. (4) Must not exceed the minimum watchdog time-out period (tTD). The watchdog circuit cannot be disabled. To avoid a reset, ST ¯¯ must be strobed. (5) Measured with VCC ≥ 2.7 V. (6) Measured with VCC < 2.7 V. |
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