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MC14018BCL Arkusz danych(PDF) 1 Page - Motorola, Inc |
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MC14018BCL Arkusz danych(HTML) 1 Page - Motorola, Inc |
1 / 6 page MOTOROLA CMOS LOGIC DATA 81 MC14018B Presettable Divide-By-N Counter The MC14018B contains five Johnson counter stages which are asynchronously presettable and resettable. The counters are synchronous, and increment on the positive going edge of the clock. Presetting is accomplished by a logic 1 on the preset enable input. Data on the Jam inputs will then be transferred to their respective Q outputs (inverted). A logic 1 on the reset input will cause all Q outputs to go to a logic 1 state. Division by any number from 2 to 10 can be accomplished by connecting appropriate Q outputs to the data input, as shown in the Function Selection table. Anti–lock gating is included in the MC14018B to assure proper counting sequence. • Fully Static Operation • Schmitt Trigger on Clock Input • Capable of Driving Two Low–power TTL Loads or One Low–power Schottky TTL Load Over the Rated Temperature Range • Pin–for–Pin Replacement for CD4018B MAXIMUM RATINGS* (Voltages Referenced to VSS) Symbol Parameter Value Unit VDD DC Supply Voltage – 0.5 to + 18.0 V Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V lin, lout Input or Output Current (DC or Transient), per Pin ± 10 mA PD Power Dissipation, per Package† 500 mW Tstg Storage Temperature – 65 to + 150 _C TL Lead Temperature (8–Second Soldering) 260 _C * Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/ _C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/ _C From 100_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. MOTOROLA SEMICONDUCTOR TECHNICAL DATA © Motorola, Inc. 1995 REV 3 1/94 MC14018B L SUFFIX CERAMIC CASE 620 ORDERING INFORMATION MC14XXXBCP Plastic MC14XXXBCL Ceramic MC14XXXBD SOIC TA = – 55° to 125°C for all packages. P SUFFIX PLASTIC CASE 648 D SUFFIX SOIC CASE 751B PIN ASSIGNMENT FUNCTIONAL TRUTH TABLE Preset Jam Clock Reset Enable Input Qn 0 0 X Qn 0 0 X Dn* X 0 1 0 1 X 0 1 1 0 X 1 X X 1 * Dn is the Data input for that stage. Stage 1 has Data brought out to Pin 1. 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 JAM 5 Q5 C R VDD JAM 4 PE Q4 Q2 JAM 2 JAM 1 Din VSS JAM 3 Q3 Q1 |
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