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MC14027B Arkusz danych(PDF) 1 Page - Motorola, Inc |
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MC14027B Arkusz danych(HTML) 1 Page - Motorola, Inc |
1 / 6 page MOTOROLA CMOS LOGIC DATA 107 MC14027B Dual J-K Flip-Flop The MC14027B dual J–K flip–flop has independent J, K, Clock (C), Set (S) and Reset (R) inputs for each flip–flop. These devices may be used in control, register, or toggle functions. • Diode Protection on All Inputs • Supply Voltage Range = 3.0 Vdc to 18 Vdc • Logic Swing Independent of Fanout • Logic Edge–Clocked Flip–Flop Design — Logic state is retained indefinitely with clock level either high or low; information is transferred to the output only on the positive–going edge of the clock pulse • Capable of Driving Two Low–power TTL Loads or One Low–power Schottky TTL Load Over the Rated Temperature Range • Pin–for–Pin Replacement for CD4027B MAXIMUM RATINGS* (Voltages Referenced to VSS) Symbol Parameter Value Unit VDD DC Supply Voltage – 0.5 to + 18.0 V Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V lin, lout Input or Output Current (DC or Transient), per Pin ± 10 mA PD Power Dissipation, per Package† 500 mW Tstg Storage Temperature – 65 to + 150 _C TL Lead Temperature (8–Second Soldering) 260 _C * Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/ _C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/ _C From 100_C To 125_C TRUTH TABLE Inputs Outputs* C† J K S R Qn‡ Qn+1 Qn+1 1 X 0 0 0 1 0 X 0 0 0 1 1 0 0 X 0 0 0 0 1 X 1 0 0 1 0 1 1 1 0 0 Qo Qo Qo X X 0 0 X Qn Qn X X X 1 0 X 1 0 X X X 0 1 X 0 1 X X X 1 1 X 1 1 X = Don’t Care ‡ = Present State † = Level Change * = Next State This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. No Change MOTOROLA SEMICONDUCTOR TECHNICAL DATA © Motorola, Inc. 1995 REV 3 1/94 MC14025B (see Page 6-5) MC14025UB (see Page 6-14) MC14027B L SUFFIX CERAMIC CASE 620 ORDERING INFORMATION MC14XXXBCP Plastic MC14XXXBCL Ceramic MC14XXXBD SOIC TA = – 55° to 125°C for all packages. P SUFFIX PLASTIC CASE 648 D SUFFIX SOIC CASE 751B BLOCK DIAGRAM 12 11 13 10 9 4 5 3 6 7 14 15 2 1 S S R R K C J K C J Q Q Q Q VDD = PIN 16 VSS = PIN 8 |
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