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MC14034 Arkusz danych(PDF) 4 Page - Motorola, Inc

Numer części MC14034
Szczegółowy opis  8-Bit Universal Bus Register
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Producent  MOTOROLA [Motorola, Inc]
Strona internetowa  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

MC14034 Arkusz danych(HTML) 4 Page - Motorola, Inc

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MOTOROLA CMOS LOGIC DATA
MC14034B
138
EXPANDED BLOCK DIAGRAM
SERIAL DATA INPUT
PARALLEL/SERIAL P/S
A/B
ENABLE A
ASYN/SYN A/S
CLOCK
CONTROL
LOGIC
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
DATA
DATA
8–BIT REGISTER
OPERATING CHARACTERISTICS
The MC14034B is composed of eight register cells con-
nected in cascade with additional control logic. Each register
cell is composed of one “D” master–slave flip–flop with sepa-
rate internal clocks, and two data transfer gates allowing the
data to be transferred bi–directionally from bus A to bus B
and from bus B to bus A, and to be memorized. Besides the
single phase clock and the serial data inputs, the control log-
ic provides four other features:
A Enable Input — When high, this input enables the bus A
data lines.
A/B Input (Data A or B) — This input controls the direc-
tion of data flow: when high, the data flows from bus A to bus
B; when low, the data flows from bus B to bus A.
P/S Input (Parallel/Serial) — This input controls the data
input mode (parallel or serial). When high, the data is trans-
ferred to the register in a parallel asynchronous mode or a
parallel synchronous mode (positive clock transition). When
low, the data is entered into the register in a serial synchro-
nous mode (positive clock transition).
A/S Input (Asynchronous/Synchronous to the Clock)
— When this input is high, the data is transferred indepen-
dently from the clock rate; when low, the clock is enabled and
the data is transferred synchronously.
LOGIC DIAGRAM
A ENABLE
9
A/B 11
SERIAL DATA 10
PARALLEL SERIAL 13
ASYN/SYN 14
CLOCK 15
CM
*D FLIP FLOP
VDD
CS
VDD
A1
16
A2
17
A3
18
A4
19
A5
20
A6
21
A7
22
A8
23
VDD
6 STAGES
(SAME AS
STAGE 1)
*D
FLIP–
FLOP
D
CM CS
Q
8
B1
7
B2
6
B3
5
B4
4
B5
3
B6
2
B7
1
B8


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