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MC14035B Arkusz danych(PDF) 1 Page - Motorola, Inc |
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MC14035B Arkusz danych(HTML) 1 Page - Motorola, Inc |
1 / 6 page MOTOROLA CMOS LOGIC DATA MC14035B 144 4-Bit Parallel-In/Parallel-Out Shift Register The MC14035B 4–bit shift register is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. It consists of a 4–stage clocked serial–shift register with synchronous parallel inputs and buffered parallel outputs. The Parallel/Serial (P/S) input allows serial–right shifting of data or synchronous parallel loading via inputs DP0 thru DP3. The True/Complement (T/C) input determines whether the outputs display the Q or Q outputs of the flip–flop stages. J–K logic forms the serial input to the first stage. With the J and K inputs connected together they operate as a serial “D” input. This device may be effectively used for shift–right/shift–left registers, parallel–to–serial/serial–to–parallel conversion, sequence generation, up/ down Johnson or ring counters, pseudo–random code generation, frequen- cy and phase comparators, sample and hold registers, etc . . . • 4–Stage Clocked Serial–Shift Operation • Synchronous Parallel Loading of all Four Stages • J–K Serial Inputs on First Stage • Asynchronous True/Complement Control of all Outputs • Fully Static Operation • Asynchronous Master Reset • Data Transfer Occurs on the Positive–Going Clock Transition • No Limit on Clock Rise and Fall Times • All Inputs are Buffered • Supply Voltage Range = 3.0 Vdc to 18 Vdc • Capable of Driving Two Low–power TTL Loads or One Low–power Schottky TTL Load Over the Rated Temperature Range MAXIMUM RATINGS* (Voltages Referenced to VSS) Symbol Parameter Value Unit VDD DC Supply Voltage – 0.5 to + 18.0 V Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V lin, lout Input or Output Current (DC or Transient), per Pin ± 10 mA PD Power Dissipation, per Package† 500 mW Tstg Storage Temperature – 65 to + 150 _C TL Lead Temperature (8–Second Soldering) 260 _C * Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/ _C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/ _C From 100_C To 125_C TRUTH TABLE Inputs tn Output Q0 C J K R tn Output Q0 0 0 0 0 0 1 0 Q0 (n – 1) 1 0 0 Q0 (n – 1) 1 1 0 1 X X 0 Q0 (n – 1) X X X 1 0 X = Don’t Care P/S = 0 = Serial Mode T/C = 1 = True Outputs MOTOROLA SEMICONDUCTOR TECHNICAL DATA © Motorola, Inc. 1995 REV 3 1/94 MC14035B L SUFFIX CERAMIC CASE 620 ORDERING INFORMATION MC14XXXBCP Plastic MC14XXXBCL Ceramic MC14XXXBD SOIC TA = – 55° to 125°C for all packages. P SUFFIX PLASTIC CASE 648 D SUFFIX SOIC CASE 751B PIN ASSIGNMENT 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 DP3 Q3 Q2 Q1 VDD DP0 DP1 DP2 J K T/C Q0 VSS P/S C R |
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