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MC14035B Arkusz danych(PDF) 3 Page - Motorola, Inc |
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MC14035B Arkusz danych(HTML) 3 Page - Motorola, Inc |
3 / 6 page MOTOROLA CMOS LOGIC DATA MC14035B 146 SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C, See Figure 1) Characteristic Symbol VDD Vdc Min Typ # Max Unit Output Rise and Fall Time TTLH, TTHL = (1.5 ns/pF) CL + 25 ns TTLH, TTHL = (0.75 ns/pF) CL + 12.5 ns TTLH, TTHL = (0.55 ns/pF) CL + 12.5 ns tTLH, tTHL 5.0 10 15 — — — 100 50 40 200 100 80 ns Propagation Delay Time, Clock or Reset to Q TPLH, TPHL = (1.75 ns/pF) CL + 223 ns TPLH, TPHL = (0.70 ns/pF) CL + 89 ns TPLH, TPHL = (0.53 ns/pF) CL + 67 ns tPLH, tPHL 5.0 10 15 — — — 300 130 95 600 260 190 ns Clock Pulse Width tWH 5.0 10 15 335 165 125 135 45 40 — — — ns Reset Pulse Width tWH 5.0 10 15 400 175 130 80 40 35 — — — ns Reset Removal Time trem 5.0 10 15 80 30 25 40 15 10 — — — ns Clock Pulse Rise and Fall Time tTLH, tTHL 5.0 10 15 No Limit — Clock Pulse Frequency fcl 5.0 10 15 — — — 2.5 6.0 10 1.2 2.0 3.0 MHz J–K to Clock Setup Time tsu 5.0 10 15 500 200 150 120 50 30 — — — ns Clock to J–K Hold Time th 5.0 10 15 40 30 25 – 40 – 5 0 — — — ns P/S to Clock Setup Time tsu 5.0 10 15 500 200 150 25 10 7.5 — — — ns Clock to P/S Hold Time th 5.0 10 15 30 20 20 – 70 – 20 – 10 — — — ns DP to Clock Setup Time tsu 5.0 10 15 500 200 150 90 20 15 — — — ns Clock to DP Hold Time th 5.0 10 15 90 40 40 – 25 0 5 — — — ns * The formulas given are for the typical characteristics only at 25 _C. #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. Figure 1. Timing Diagram RESET 50% trem CLOCK INPUT J–K INPUT P/S INPUT DP0 INPUT Q0 T/C INPUT LOW 50% 50% 50% tWH 1/fcl th tsu tsu tsu th tTHL tTLH th tsu 90% 10% 50% tPHL tPLH tPHL tPLH 50% |
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