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CDCUA877ZQLR Arkusz danych(PDF) 4 Page - Texas Instruments

Numer części CDCUA877ZQLR
Szczegółowy opis  1.8-V PHASE LOCK LOOP CLOCK DRIVER
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CDCUA877ZQLR Arkusz danych(HTML) 4 Page - Texas Instruments

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ABSOLUTE MAXIMUM RATINGS
CDCUA877
SCAS769A – AUGUST 2006 – REVISED JUNE 2007
Figure 1. Logic Diagram (Positive Logic)
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
UNIT
VDDQ
Supply voltage range
–0.5 to 2.5
V
AVDD
VI
Input voltage range(2) (3)
–0.5 to VDDQ + 0.5
V
VO
Output voltage range(2) (3)
–0.5 to VDDQ + 0.5
V
IIK
Input clamp current, (VI < 0 or VI > VDDQ)
±50
mA
IOK
Output clamp voltage, (VO < 0 or VO > VDDQ)
±50
mA
IO
Continuous output current, (VO = 0 to VDDQ)
±50
mA
IDDC
Continuous current through each VDDQ or GND
±100
mA
No airflow
151.9
RθJA
Thermal resistance, junction-to-ambient(4)
Airllflow 150 ft/min
146.1
K/W
RθJC
Thermal resistance, junction-to-case(4)
No airflow
102.4
TSTG
Storage temperature range
–65 to 150
°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3)
This value is limited to 2.5 V maximum.
(4)
The package thermal impedance is calculated in accordance with JESD51 and JEDEC2S1P (high-k board).
4
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