ADS8201

SLAS534B – JULY 2009 – REVISED MAY 2010

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THEORY OF OPERATION

The ADS8201 is a low-power data acquisition system that includes a 12-bit successive approximation register

(SAR) analog-to-digital converter (ADC), eight-channel mux, and a first-in first-out (FIFO) buffer. The SAR

architecture is based on charge redistribution, which inherently includes a sample/hold (S/H) function.

The ADS8201 uses an internal clock to run the conversions.

The ADS8201 has eight analog inputs. The analog inputs are either single-ended or differential, depending on

the channel configuration. When a conversion is initiated, the input on these pins is sampled on the internal

capacitor array. While a conversion is in progress, the inputs are disconnected from any internal function. The

device can be programmed for manual channel selection or programmed into an auto-channel select mode that

A programmable gain amplifier (PGA) allows for a gain selection of 1, 2, 4, or 8. Individual channels can be

programmed to different gains. This feature allows the ADS8201 to be used in a wide range of applications. The

channel gain mapping feature is very useful in applications where different sensors around different

common-mode voltages must be digitized. Appropriate gain settings can also be chosen to take advantage of the

full range of the converter.

ANALOG INPUT

When the converter enters the hold mode, the voltage on the analog input channel of interest is captured on the

internal capacitor array. The input span is limited to the range of 0.1V to (VA – 0.1V). The PGA front-end

provides a high input impedance that removes the loading effect issues typically associated with high source

impedances.

Care must be taken regarding the absolute analog input voltage. To maintain converter linearity, the +IN and –IN

inputs and the span of [+IN – (–IN)] should be within the limits specified. Exceeding these ranges may cause the

converter linearity to not meet its stated specifications. To minimize noise, use low bandwidth input signals with

low-pass filters.

Care should also be taken to ensure that the output impedance of the sources driving the +IN and –IN inputs are

matched. If this matching is not observed, the two inputs could have different settling times. These different times

may result in offset error, gain error, and linearity error, which all change with temperature and input voltage.

PROGRAMMABLE GAIN AMPLIFIER (PGA)

The ADS8201 features an integrated PGA with gain options of 1, 2, 4, and 8. Each individual channel can be

configured for different gain settings depending on the application. An appropriate gain should be chosen for

each application to take advantage of the full range of the converter.

At power-up, the system settling time is approximately 40ms. This period includes the PGA turn-on time and

settling time to a 12-bit level. Once the device has been configured, the PGA settling time during channel

switching is optimized to provide a throughput of 100k samples-per-second (SPS) in auto-trigger and

auto-channel update modes.

The ADS8201 also provides a PGAOUT pin that can be used for further signal conditioning before inputting to

the ADC. If no additional conditioning is required, the PGAOUT pin should be tied to the ADCIN pin.

BIPOLAR/UNIPOLAR OPERATION

The PGAREF pin allows the ADS8201 to be operated in true differential and bipolar modes. This type of

operation is achieved by setting the PGAREF pin. If this pin is set to GND, the device operates in unipolar mode.

configured in differential mode. See the Application Information section for an example of a typical circuit

diagram.

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