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TPD2EUSB30DRTR Arkusz danych(PDF) 5 Page - Texas Instruments |
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TPD2EUSB30DRTR Arkusz danych(HTML) 5 Page - Texas Instruments |
5 / 15 page 1-mm GND D+ D- 1-mm 1-mm GND D+ D- TPD2EUSB30DRTR TX+ TX- GND RX+ RX- VBUS D- D+ GND 8-mm USB 3.0 Host/ Controller TX+ TX- GND RX+ RX- VBUS D- D+ GND USB 3.0 Host/ Controller 8-mm 1-mm 1-mm 1-mm TPD4EUSB30 D1+ D1- GND GND D2+ D2- One TPD4EUSB30 & One TPD2EUSB30 to Protect USB3.0 Class A connec tor (Two Layer Routing) Three TPD2EUSB30 to Protect USB3.0 Class A connector (One Layer Routing) N.C. N.C. N.C. N.C. TPD2EUSB30, TPD4EUSB30 www.ti.com SLVSAC2 – AUGUST 2010 APPLICATION INFORMATION Layout Guide with TPDxEUSB30DRTR Refer to Figure 7, the TPD2EUSB30DRTR is offered in space saving DRT package. The DRT package is a 1mm* 1mm package with flow-through pin-mapping for the high-speed differential lines. The TPD4EUSB30DRTR is offered in space saving DQA package. The DQA is a 1mm* 2.5mm package with flow-through pin-mapping for the high-speed differential lines. It is recommended to place the package right next to the USB 3.0 connector. The GND pin should connected to GND plane of the board through a large VIA. If a dedicated GND plane is not present right underneath, it is recommended to route to the GND plane through a wide trace. The current associated with IEC ESD stress can be in the range of 30Amps or higher momentarily. A good, low impedance GND path ensures the system robustness against IEC ESD stress. The TPDxEUSB30 can provide system level ESD protection to the high-speed differential ports (>6 Gbps data rate). The flow-through package offers flexibility for board routing with traces up to 15 mills wide. It allows the differential signal pairs couple together right after they touch the ESD ports of the TPDxEUSB30. Figure 7. Layout Guide with the TPDxEUSB30 at the USB3.0 Class A Connector TPDxEUSB30 Eye Pattern Test See Figure 9 for a demonstration of the TPDxEUSB30 performance the lab set-up. Figure 8 shows a lab board that was designed to demonstrate the degradation of the eye pattern quality with and without the TPD2EUSB30 in the USB 3.0 signal path. Figure 10 shows that there is only ~2 ps jitter penalty to the differential signal when the TPD2EUSB30 device was added in the signal path. Similar setup was employed to measure eye pattern for the TPD4EUSB30. Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): TPD2EUSB30, TPD4EUSB30 |
Podobny numer części - TPD2EUSB30DRTR |
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Podobny opis - TPD2EUSB30DRTR |
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