CDCE906PWR datasheet(7/42 Pages) TI

Numer części	CDCE906PWR

Szczegółowy opis	PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER

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CDCE906

SCAS814H – NOVEMBER 2005 – REVISED DECEMBER 2007

DEVICE CHARACTERISTICS (continued)

over recommended operating free-air temperature range and test load (unless otherwise noted), see Figure 1

PARAMETER

TEST CONDITIONS

MIN TYP(1)

MAX

UNIT

1 PLL, 1 Output

fOUT = 24.576 MHz

65

95

tjit(cc)

Cycle-to-cycle jitter (5) (6)

ps

3 PLLs, 3 Outputs

fOUT = 24.576 MHz

85

135

1 PLL, 1 Output

fOUT = 24.576 MHz

90

115

tjit(per)

Peak-to-peak period jitter(5)(6)

ps

3 PLLs, 3 Outputs

fOUT = 24.576 MHz

100

150

Output skew (see (7) and Table 5)

1.6-ns rise/fall time at

tsk(o)

200

ps

fvco = 150 MHz, Pdiv = 3

odc

Output duty cycle(8)

fvco = 100 MHz, Pdiv = 1

45%

55%

LVCMOS PARAMETER FOR Vccout = 2.5-V Mode

(9)

Vccout = 2.3 V, IOH = 0.1 mA

2.2

VOH

LVCMOS high-level output voltage

Vccout = 2.3 V, IOH = –3 mA

1.7

V

Vccout = 2.3 V, IOH = –4 mA

1.5

Vccout = 2.3 V, IOL = 0.1 mA

0.1

VOL

LVCMOS low-level output voltage

Vccout = 2.3 V, IOL = 3 mA

0.5

V

Vccout = 2.3 V, IOL = 4 mA

0.85

All PLL bypass

9

tPLH,

Propagation delay

ns

tPHL

VCO bypass

11

Rise and fall time for output

tr0/tf0

Vccout = 2.5 V (20%–80%)

2

3.9

5.6

ns

slew rate 0

Rise and fall time for output

tr1/tf1

Vccout = 2.5 V (20%–80%)

1.8

2.9

4.4

ns

slew rate 1

Rise and fall time for output

tr2/tf2

Vccout = 2.5 V (20%–80%)

1.3

2

3.2

ns

slew rate 2

Rise and fall time for output

tr3/tf3

Vccout = 2.5 V (20%–80%)

0.4

0.8

1.1

ns

slew rate 3 (Default Configuration)

1 PLL, 1 Output

fOUT = 24.576 MHz

85

120

tjit(cc)

Cycle-to-cycle jitter (10) (11)

ps

3 PLLs, 3 Outputs

fOUT = 24.576 MHz

95

155

1 PLL, 1 Output

fOUT = 24.576 MHz

110

135

tjit(per)

Peak-to-peak period jitter (10)(11)

ps

3 PLLs, 3 Outputs

fOUT = 24.576 MHz

110

175

2-ns rise/fall time at

tsk(o)

Output skew (see (12) and Table 5)

250

ps

fVCO = 150 MHz, Pdiv = 3

odc

Output duty cycle(13)

fVCO = 100 MHz, Pdiv = 1

45%

55%

SMBus PARAMETER

SCLK and SDATA input clamp

VIK

VCC = 3 V, II = –18 mA

–1.2

V

voltage

II

SCLK and SDATA input current

VI = 0 V or VCC, VCC = 3.6 V

±5

µA

VIH

SCLK input high voltage

2.1

V

VIL

SCLK input low voltage

0.8

V

VOL

SDATA low-level output voltage

IOL = 4 mA, VCC = 3 V

0.4

V

CISCLK

Input capacitance at SCLK

VI = 0 V or VCC

3

10

pF

CISDATA Input capacitance at SDATA

VI = 0 V or VCC

3

10

pF

(5)

50000 cycles.

(6)

Jitter depends on configuration. Jitter data is for normal tr/tf, input frequency = 27 MHz, fVCO = 147 MHz output.

(7)

The tsk(o) specification is only valid for equal loading of all outputs.

(8)

odc depends on output rise and fall time (tr/tf); above limits are for normal tr/tf.

(9)

There is a limited drive capability at output supply voltage of 2.5 V. For proper termination, see application report SCAA080.

(10) 50000 cycles.

(11) Jitter depends on configuration. Jitter data is for normal tr/tf, input frequency = 27 MHz, fVCO = 147 MHz output.

(12) The tsk(o) specification is only valid for equal loading of all outputs.

(13) odc depends on output rise and fall time (tr/tf); above limits are for normal tr/tf.

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