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SA2007HSA Arkusz danych(PDF) 6 Page - Sames |
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SA2007HSA Arkusz danych(HTML) 6 Page - Sames |
6 / 10 page sames sames SA2007H 6/10 http://www.sames.co.za Figure 5: Measured energy direction on D1 or D2 Figure 6: Mains zero crossing on FMO Figure 7: Output signals in latched mode P1 P2 INT RP FMO dr-01621 D1, D2 V I DR-01283 t DIR t t t DR-01284 FMO MAINS t V t t Positive energy flow, when voltage sense and both current sense input are in phase, is indicated on pin D1 or D2 as a logic 1. Figure 5 shows the behavior of D1 and D2, when energy reversal takes place. The time period for the direction signal to change state, t , is the time it takes for the internal integrator DIR to count (down) from its present value to zero. Thus the energy consumption rate determines the speed of change on the direction outputs. Mains zero crossing indication (FMO) The square wave signal of FMO indicates the polarity of the mains voltage. Due to comparator offsets, the FMO low to high transition can occur within a range as shown in figure 6. The time between successive low to high transitions will be equal to the mains voltage period. Interrupt (INT) While the SA2007H is operating in latched mode (see Output mode description) an interrupt is generated with the falling edge of the pulse outputs P1 and P2 (see figure 7). INT is cleared with a logic 1 on the RP input. OUTPUT SIGNALS IN LATCHED MODE Latched mode is selected by setting the OMODE input to logic 1. This mode is used with a micro controller to ensure that any simultaneous pulses on P1 and P2 are not missed. The functionality of the latched mode is shown in figure 7. An interrupt is generated with a falling edge on any of the pulse output signals P1 and P2. The micro controller needs to scan the status of the pulse outputs as well as the direction signals D1 and D2 during its interrupt service routine. The micro controller clears the interrupt by setting the RP input to a logic 1. The pulse outputs P1 and P2 are cleared along with the interrupt. Note that energy pulses are inhibited when the interrupt output is set (during latched mode). PRELIMINARY |
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