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KM4132G271A-12 Arkusz danych(PDF) 1 Page - Samsung semiconductor |
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KM4132G271A-12 Arkusz danych(HTML) 1 Page - Samsung semiconductor |
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1 / 48 page  KM4132G271A CMOS SGRAM Rev.0 (August 1997) The KM4132G271A is 8,388,608 bits synchronous high data rate Dynamic RAM organized as 2 x 131,072 words by 32 bits, fabricated with SAMSUNG's high performance CMOS technol- ogy. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length, and programmable latencies allows the same device to be useful for a variety of high bandwidth, high perfor- mance memory system applications. Write per bit and 8 columns block write improves performance in graphics systems. ¡Ü JEDEC standard 3.3V power supply ¡Ü LVTTL compatible with multiplexed address ¡Ü Dual bank / Pulse RAS ¡Ü MRS cycle with address key programs -. CAS Latency (2, 3) -. Burst Length (1, 2, 4, 8 & full page) -. Burst Type (Sequential & Interleave) ¡Ü All inputs are sampled at the positive going edge of the system clock ¡Ü Burst Read Single-bit Write operation ¡Ü DQM 0-3 for byte masking ¡Ü Auto & self refresh ¡Ü 16ms refresh period (1K cycle) ¡Ü 100 Pin QFP Graphics Features ¡Ü SMRS cycle. -. Load mask register -. Load color register ¡Ü Write Per Bit(Old Mask) ¡Ü Block Write(8 Columns) GENERAL DESCRIPTION FEATURES FUNCTIONAL BLOCK DIAGRAM 128K x 32Bit x 2 Banks Synchronous Graphic RAM ORDERING INFORMATION Part NO. Cycle time Clock f Access time@CL=3 KM4132G271A-8 8ns 125MHz 7.0ns KM4132G271A-10 10ns 100MHz 7.0ns KM4132G271A-12 12ns 83MHz 9.0ns CLK CKE CS RAS CAS WE DSF DQMi BLOCK WRITE CONTROL LOGIC DQi 128Kx32 CELL ARRAY 128Kx32 CELL ARRAY SERIAL COUNTER COLUMN ADDRESS BUFFER ROW DECORDER BANK SELECTION ADDRESS REGISTER REFRESH COUNTER ROW ADDRESS BUFFER MASK REGISTER COLOR REGISTER MUX WRITE CONTROL LOGIC COLUMN MASK (i=0~31) DQMi CLOCK ADDRESS(A0~A9) DQMi |
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