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TPA3111D1_101 Arkusz danych(PDF) 2 Page - Texas Instruments |
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TPA3111D1_101 Arkusz danych(HTML) 2 Page - Texas Instruments |
2 / 27 page TPA3111D1 SLOS618B – AUGUST 2009 – REVISED AUGUST 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT VCC Supply voltage AVCC, PVCC –0.3 V to 30 V SD, FAULT,GAIN0, GAIN1 –0.3 V to VCC + 0.3 V VI Interface pin voltage PLIMIT –0.3 V toGVDD + 0.3 V INN, INP –0.3 V to 6.3 V Continuous total power dissipation See Thermal Inforamtion Table TA Operating free-air temperature range –40°C to 85°C TJ Operating junction temperature range(2) –40°C to 150°C Tstg Storage temperature range –65°C to 150°C RL Minimum Load Resistance BTL 3.2 Human body model (3) (all pins) ±2 kV Electrostatic discharge Charged-device model (4) (all pins) ±500 V (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The TPA3111D1 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection shutdown. See TI Technical Briefs SCBA017D and SLUA271 for more information about using the QFN thermal pad. See TI Technical Briefs SLMA002 for more information about using the HTQFP thermal pad. (3) In accordance with JEDEC Standard 22, Test Method A114-B. (4) In accordance with JEDEC Standard 22, Test Method C101-A THERMAL INFORMATION TPA3111D1 THERMAL METRIC(1) (2) UNITS PWP (28 PINS) qJA Junction-to-ambient thermal resistance 30.3 qJCtop Junction-to-case (top) thermal resistance 33.5 qJB Junction-to-board thermal resistance 17.5 °C/W yJT Junction-to-top characterization parameter 0.9 yJB Junction-to-board characterization parameter 7.2 qJCbot Junction-to-case (bottom) thermal resistance 0.9 (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT VCC Supply voltage PVCC, AVCC 8 26 V VIH High-level input voltage SD, GAIN0, GAIN1 2 V VIL Low-level input voltage SD, GAIN0, GAIN1 0.8 V VOL Low-level output voltage FAULT, RPULLUP=100kΩ, VCC=26V 0.8 V IIH High-level input current SD, GAIN0, GAIN1, VI = 2, VCC = 18 V 50 µA IIL Low-level input current SD, GAIN0, GAIN1, VI = 0.8V, VCC = 18 V 5 µA TA Operating free-air temperature –40 85 °C 2 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPA3111D1 |
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