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ADG5436BRUZ Arkusz danych(PDF) 9 Page - Analog Devices

Numer części ADG5436BRUZ
Szczegółowy opis  High Voltage Latch-Up Proof, Dual SPDT Switches
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Strona internetowa  http://www.analog.com
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ADG5436BRUZ Arkusz danych(HTML) 9 Page - Analog Devices

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ADG5436
Rev. 0 | Page 9 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
IN1
1
S1A
2
D1
3
S1B
4
NC
16
NC
15
NC
14
VDD
13
VSS 5
S2B
12
GND
6
D2
11
NC
7
S2A
10
NC
8
IN2
9
NC = NO CONNECT
ADG5436
TOP VIEW
(Not to Scale)
Figure 3. TSSOP Pin Configuration
NOTES
1. EXPOSED PAD TIED TO SUBSTRATE, VSS.
2. NC = NO CONNECT.
PIN 1
INDICATOR
1
D1
2
S1B
3
VSS
4
GND
11 VDD
12 EN
10 S2B
9D2
TOP VIEW
(Not to Scale)
ADG5436
Figure 4. LFCSP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
TSSOP
LFCSP
Mnemonic
Function
1
15
IN1
Logic Control Input 1.
2
16
S1A
Source Terminal 1A. This pin can be an input or output.
3
1
D1
Drain Terminal 1. This pin can be an input or output.
4
2
S1B
Source Terminal 1B. This pin can be an input or output.
5
3
VSS
Most Negative Power Supply Potential.
6
4
GND
Ground (0 V) Reference.
7, 8, 14 to 16
5, 7, 13, 14
NC
No Connect.
9
6
IN2
Logic Control Input 2.
10
8
S2A
Source Terminal 2A. This pin can be an input or output.
11
9
D2
Drain Terminal 2. This pin can be an input or output.
12
10
S2B
Source Terminal 2B. This pin can be an input or output.
13
11
VDD
Most Positive Power Supply Potential.
N/A
12
EN
Active High Digital Input. When this pin is low, the device is disabled and all switches are
off. When this pin is high, INx logic inputs determine the on switches.
EP
Exposed Pad
The exposed pad is connected internally. For increased reliability of the solder joints and
maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
TRUTH TABLE FOR SWITCHES
Table 8. ADG5436 TSSOP Truth Table
INx
SxA
SxB
0
Off
On
1
On
Off
Table 9. ADG5436 LFCSP Truth Table
EN
INx
SxA
SxB
0
X
Off
Off
1
0
Off
On
1
1
On
Off


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