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AD7451ARMZ Arkusz danych(PDF) 6 Page - Analog Devices |
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AD7451ARMZ Arkusz danych(HTML) 6 Page - Analog Devices |
6 / 24 page AD7441/AD7451 Rev. D | Page 6 of 24 Parameter Test Conditions/Comments B Version Unit CONVERSION RATE Conversion Time 888 ns with an 18 MHz SCLK 16 SCLK cycles Track-and-Hold Acquisition Time1 Sine wave input 250 ns max Step input 290 ns max Throughput Rate 1 MSPS max POWER REQUIREMENTS VDD 2.7/5.25 V min/max IDD6, 7 Normal Mode (Static) SCLK on or off 0.5 mA typ Normal Mode (Operational) VDD = 4.75 V to 5.25 V 1.95 mA max VDD = 2.7 V to 3.6 V 1.45 mA max Full Power-Down Mode SCLK on or off 1 μA max Power Dissipation Normal Mode (Operational) VDD = 5 V; 1.55 mW typ for 100 ksps6 9.25 mW max VDD = 3 V; 0.6 mW typ for 100 ksps6 4 mW max Full Power-Down VDD = 5 V; SCLK on or off 5 μW max VDD = 3 V; SCLK on or off 3 μW max 1 See the Terminology section. 2 Analog inputs with slew rates exceeding 27 V/μs (full-scale input sine wave > 3.5 MHz) within the acquisition time can cause the converter to return an incorrect result. 3 A small dc input is applied to VIN– to provide a pseudo ground for VIN+. 4 The AD7441 is functional with a reference input in the range 100 mV to VDD. 5 Guaranteed by characterization. 6 See the Power vs. Throughput Rate section. 7 Measured with a full-scale dc input. |
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