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ISL12032IVZ Arkusz danych(PDF) 5 Page - Intersil Corporation |
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ISL12032IVZ Arkusz danych(HTML) 5 Page - Intersil Corporation |
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5 / 26 page  5 FN6618.0 December 14, 2007 IRQ/ACRDY/LV/EVDET (OPEN DRAIN OUTPUTS) VOL Output Low Voltage VDD = 5V, IOL = 3mA 0.4 V VDD = 2.7V, IOL = 1mA 0.4 V FOUT (CMOS OUTPUT) VOL Output Low Voltage IOH = 1mA 0.3 x VDD V VOH Output High Voltage 0.7 x VDD V EVIN IEVPU EVIN Pull-up Current VDD = 5.5V, VBAT = 3.0V 1.0 3.0 8.0 µA VDD = 0V, VBAT = 1.8V 100 600 nA VIL Input Low Voltage 0.3 x VDD V VIH Input High Voltage 0.7 x VDD V IEVPD EVIN Disabled Pull-down Current VDD = 5.5V 200 nA DC Operating Characteristics Specifications apply for: VDD = 2.7 to 5.5V, TA = -40°C to +85°C, unless otherwise stated. (Continued) SYMBOL PARAMETER CONDITIONS MIN (Note 10) TYP (Note 4) MAX (Note 10) UNITS NOTES Power-Down Timing Specifications apply for: V DD = 2.7 to 5.5V, TA = -40°C to +85°C, unless otherwise stated. SYMBOL PARAMETER CONDITIONS MIN (Note 10) TYP (Note 4) MAX (Note 10) UNITS NOTES VDD SR- VDD Negative Slew Rate 10 V/ms 6 I2C Interface Specifications Specifications apply for: VDD = 2.7 to 5.5V, TA = -40°C to +85°C, unless otherwise stated. SYMBOL PARAMETER TEST CONDITIONS MIN (Note 10) TYP (Note 4) MAX (Note 10) UNITS NOTES VIL SDA and SCL Input Buffer LOW Voltage -0.3 0.3 x VDD V VIH SDA and SCL Input Buffer HIGH Voltage 0.7 x VDD VDD + 0.3 V Hysteresis SDA and SCL Input Buffer Hysteresis 0.05 x VDD V VOL SDA Output Buffer LOW Voltage, Sinking 3mA VDD = 5V, IOL = 3mA 0.4 V CPIN SDA and SCL Pin Capacitance TA = +25°C, f = 1MHz, VDD =5V, VIN =0V, VOUT =0V 10 pF fSCL SCL Frequency 400 kHz tIN Pulse Width Suppression Time at SDA and SCL Inputs Any pulse narrower than the max spec is suppressed. 50 ns tAA SCL Falling Edge to SDA Output Data Valid SCL falling edge crossing 30% of VDD, until SDA exits the 30% to 70% of VDD window. 900 ns tBUF Time the Bus Must be Free Before the Start of a New Transmission SDA crossing 70% of VDD during a STOP condition, to SDA crossing 70% of VDD during the following START condition. 1300 ns tLOW Clock LOW Time Measured at the 30% of VDD crossing. 1300 ns tHIGH Clock HIGH Time Measured at the 70% of VDD crossing. 600 ns ISL12032 |
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