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SL3S1203FTB0 Arkusz danych(PDF) 7 Page - NXP Semiconductors |
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7 / 22 page SL3S1203_1213_SDS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product short data sheet PUBLIC Rev. 3.2 — 9 November 2010 198732 7 of 22 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 10. Mechanical specification 10.1 Wafer specification See Ref. 20 “Data sheet - Delivery type description – General specification for 8” wafer on UV-tape with electronic fail die marking, BU-ID document number: 1093**”. 10.1.1 Wafer Table 6. Specifications Wafer Designation each wafer is scribed with batch number and wafer number Diameter 200 mm (8”) Thickness 75 μm ± 15 μm Number of pads 4 Pad location non diagonal/ placed in chip corners Distance pad to pad RFN-RFP 333.0 µm Distance pad to pad OUT-RFN 383.0 µm Process CMOS 0.14 µm Batch size 25 wafers Potential good dies per wafer 130.000 Wafer backside Material Si Treatment ground and stress release Roughness Ra max. 0.5 μm, Rt max. 5 μm Chip dimensions Die size including scribe 0.485 mm × 0.435 mm = 0.211 mm2 Scribe line width: x-dimension = 15 μm y-dimension = 15 μm Passivation on front Type Sandwich structure Material PE-Nitride (on top) Thickness 1.75 μm total thickness of passivation Au bump Bump material > 99.9% pure Au Bump hardness 35 – 80 HV 0.005 Bump shear strength > 70 MPa Bump height 18 μm Bump height uniformity within a die ± 2 μm – within a wafer ± 3 μm – wafer to wafer ± 4 μm Bump flatness ±1.5 μm |
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