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AD21462WBBZ3 Arkusz danych(PDF) 2 Page - Analog Devices |
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AD21462WBBZ3 Arkusz danych(HTML) 2 Page - Analog Devices |
2 / 60 page Rev. PrA | Page 2 of 60 | November 2008 ADSP-21462W/ADSP-21465W/ADSP-21467 Preliminary Technical Data KEY FEATURES—PROCESSOR CORE At up to 450 MHz core instruction rate, the processor per- forms at 2.7 GFLOPS/900 MMACs 5 Mbits on-chip RAM, 4 Mbits on-chip ROM for simultaneous access by the core processor and DMA DDR2 DRAM interface (16-bit) operating at maximum fre- quency of half the core clock frequency Dual data address generators (DAGs) with modulo and bit- reverse addressing Zero-overhead looping with single-cycle loop setup, provid- ing efficient program sequencing VISA (variable instruction set) execution support Single instruction multiple data (SIMD) architecture provides: Two computational processing elements Concurrent execution Code compatibility with other SHARC family members at the assembly level Parallelism in buses and computational units allows: Single cycle executions (with or without SIMD) of a mul- tiply operation, an ALU operation, a dual memory read or write, and an instruction fetch Transfers between memory and core at a sustained 7.2 Gbytes/second bandwidth FFT accelerator implements radix-2 complex/real input, com- plex output FFT with no core intervention IIR accelerators perform dedicated IIR filtering with high-per- formance, fixed- and floating-point processing capabilities with no core intervention FIR accelerators perform dedicated FIR filtering with high- performance, fixed- and floating-point processing capabil- ities with no core intervention Program sequencer can execute code directly from external memory bank 0 (SRAM, as well as DDR2 DRAM). This allows more options to a user in terms of code storage. New opcodes of 16 and 32 bits are supported in addition to the existing 48 bit opcodes. Variable Instruction Set Archi- tecture (VISA) execution from external DDR2 DRAM memory is also supported. INPUT/OUTPUT FEATURES Two 8-bit wide link ports can connect to the link ports of other SHARCs or peripherals. Link ports are bidirectional programmable ports having eight data lines, an acknowl- edge line and a clock line DMA controller supports 67 DMA channels for transfers between internal memory and a variety of peripherals DMA transfers at peripheral clock speed, in parallel with full-speed processor execution External port provides glueless connection to 16-bit wide synchronous DDR2 DRAM using a dedicated DDR2 DRAM controller, and 8-bit wide asynchronous memory devices using asynchronous memory interface (AMI) Programmable wait state options (for AMI) 2 to 31 DDR2_CLK cycles Delay-line DMA engine maintains circular buffers in exter- nal memory with tap/offset based reads 16-bit data access for synchronous DDR2 DRAM memory 8-bit data access for asynchronous memory 4 memory select lines allows multiple external memory devices Digital audio interface (DAI) includes eight serial ports, four precision clock generators, an input data port, an S/PDIF transceiver, and a signal routing unit Digital peripheral interface (DPI) includes, two timers, one UART, and two SPI ports, a DTCP cipher (ADSP-21462W and ADSP-21465W), and a two-wire interface port Outputs of PCG A and B can be routed through DAI pins Outputs of PCG C and D can be driven on to DAI as well as DPI pins Eight dual data line serial ports — each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair TDM support for telecommunications interfaces including 128 TDM channel support for newer telephony interfaces such as H.100/H.110 Up to 16 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port (IDP), configurable as eight channels of serial data or seven channels of serial data and up to a 20-bit wide parallel data channel Signal routing unit provides configurable and flexible con- nections between the various peripherals and the DAI/DPI components 4 independent asynchronous sample rate converters (ASRC). Each converter has separate serial input and output ports, a de-emphasis filter providing up to –128 dB SNR perfor- mance, stereo sample rate converter and supports left- justified, I2S, TDM, and right-justified modes and 24-, 20-, 18-, and 16-audio data word lengths. An MLB (media local bus) interface allows the processor to support for both 3-pin as well as 5-pin media local bus pro- tocols (ADSP-21462W and ADSP-21465W). 2 muxed flag/IRQ lines 1 muxed flag/IRQ /AMI_MS pin 1 muxed flag/Timer expired line /AMI_MS pin S/PDIF-compatible digital audio receiver/transmitter sup- ports EIAJ CP-340 (CP-1201), IEC-958, AES/EBU standards Left-justified, I2S or right-justified serial data input with 16-, 18-, 20- or 24-bit word widths (transmitter) Pulse-width modulation provides: 16 PWM outputs configured as four groups of four outputs supports center-aligned or edge-aligned PWM waveforms PLL has a wide variety of software and hardware multi- plier/divider ratios Thermal diode to monitor die temperature Available in 19 mm by 19 mm PBGA package (see Ordering Guide on Page 59) |
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