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ADSP-BF504F Arkusz danych(PDF) 10 Page - Analog Devices |
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ADSP-BF504F Arkusz danych(HTML) 10 Page - Analog Devices |
10 / 80 page Rev. PrC | Page 10 of 80 | January 2010 ADSP-BF504/F,ADSP-BF506F Preliminary Technical Data The timer units can be used in conjunction with the two UARTs to measure the width of the pulses in the data stream to provide a software auto-baud detect function for the respective serial channels. The timers can generate interrupts to the processor core provid- ing periodic events for synchronization, either to the system clock or to a count of external signals. In addition to the eight general-purpose programmable timers, a ninth timer is also provided. This extra timer is clocked by the internal processor clock and is typically used as a system tick clock for generation of operating system periodic interrupts. UP/DOWN COUNTERS AND THUMBWHEEL INTERFACES Two 32-bit up/down counters are provided that can sense 2-bit quadrature or binary codes as typically emitted by industrial drives or manual thumbwheels. The counters can also operate in general-purpose up/down count modes. Then, count direc- tion is either controlled by a level-sensitive input pin or by two edge detectors. A third counter input can provide flexible zero marker support and can alternatively be used to input the push-button signal of thumb wheels. All three pins have a programmable debouncing circuit. Internal signals forwarded to each timer unit enable these tim- ers to measure the intervals between count events. Boundary registers enable auto-zero operation or simple system warning by interrupts when programmable count values are exceeded. 3-PHASE PWM UNITS The two/dual 3-phase PWM generation units each feature: • 16-bit center-based PWM generation unit •Programmable PWM pulse width • Single/double update modes • Programmable dead time and switching frequency • Twos-complement implementation which permits smooth transition to full ON and full OFF states • Possibility to synchronize the PWM generation to either externally-generated or internally-generated synchroniza- tion pulses • Special provisions for BDCM operation (crossover and output enable functions) • Wide variety of special switched reluctance (SR) operating modes • Output polarity and clock gating control • Dedicated asynchronous PWM shutdown signal Each PWM block integrates a flexible and programmable 3-phase PWM waveform generator that can be programmed to generate the required switching patterns to drive a 3-phase volt- age source inverter for ac induction motor (ACIM) or permanent magnet synchronous motor (PMSM) control. In addition, the PWM block contains special functions that con- siderably simplify the generation of the required PWM switching patterns for control of the electronically commutated motor (ECM) or brushless dc motor (BDCM). Software can enable a special mode for switched reluctance motors (SRM). The six PWM output signals (per PWM unit) consist of three high-side drive signals (PWMx_AH, PWMx_BH, and PWMx_CH) and three low-side drive signals (PWMx_AL, PWMx_BL, and PWMx_CL). The polarity of the generated PWM signal can be set with software, so that either active HI or active LO PWM patterns can be produced. The switching frequency of the generated PWM pattern is pro- grammable using the 16-bit PWM_TM register. The PWM generator can operate in single update mode or double update mode. In single update mode, the duty cycle values are pro- grammable only once per PWM period, so that the resultant PWM patterns are symmetrical about the midpoint of the PWM period. In the double update mode, a second updating of the PWM registers is implemented at the midpoint of the PWM period. In this mode, it is possible to produce asymmetrical PWM patterns that produce lower harmonic distortion in 3-phase PWM inverters. Pulses synchronous to the switching frequency can be generated internally and output on the PWMx_SYNC pin. The PWM unit can also accept externally generated synchronization pulses through PWMx_SYNC. Each PWM unit features a dedicated asynchronous shutdown pin, PWMx_TRIP, which (when brought low) instantaneously places all six PWM outputs in the OFF state. SERIAL PORTS The processors incorporate two dual-channel synchronous serial ports (SPORT0 and SPORT1) for serial and multiproces- sor communications. The SPORTs support the following features: •I2S capable operation. • Bidirectional operation – Each SPORT has two sets of inde- pendent transmit and receive pins, enabling eight channels of I2S stereo audio. • Buffered (8-deep) transmit and receive ports – Each port has a data register for transferring data words to and from other processor components and shift registers for shifting data in and out of the data registers. • Clocking – Each transmit and receive port can either use an external serial clock or generate its own, in frequencies ranging from (fSCLK/131,070) Hz to (fSCLK/2) Hz. • Word length – Each SPORT supports serial data words from 3 to 32 bits in length, transferred most-significant-bit first or least-significant-bit first. • Framing – Each transmit and receive port can run with or without frame sync signals for each data word. Frame sync signals can be generated internally or externally, active high or low, and with either of two pulse widths and early or late frame sync. |
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Podobny opis - ADSP-BF504F |
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