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ADC1415S125 Arkusz danych(PDF) 2 Page - NXP Semiconductors

Numer części ADC1415S125
Szczegółowy opis  Single 14-bit ADC 65, 80, 105 or 125 Msps with Input Buffer CMOS or LVDS DDR digital outputs
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ADC1415S065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 4 June 2009
2 of 33
NXP Semiconductors
ADC1415S065/080/105/125
Single 14-bit ADC 65, 80, 105 or 125 Msps with input buffer
4.
Ordering information
5.
Block diagram
Table 1.
Ordering information
Type number
fs (Msps) Package
Name
Description
Version
ADC1415S125HN/C1 125
HVQFN40
plastic thermal enhanced very thin quad flat package; no
leads; 40 terminals; body 6
× 6 × 0.85 mm
SOT618-1
ADC1415S105HN/C1 105
HVQFN40
plastic thermal enhanced very thin quad flat package; no
leads; 40 terminals; body 6
× 6 × 0.85 mm
SOT618-1
ADC1415S080HN/C1 80
HVQFN40
plastic thermal enhanced very thin quad flat package; no
leads; 40 terminals; body 6
× 6 × 0.85 mm
SOT618-1
ADC1415S065HN/C1 65
HVQFN40
plastic thermal enhanced very thin quad flat package; no
leads; 40 terminals; body 6
× 6 × 0.85 mm
SOT618-1
Fig 1.
Block diagram
ADC1415S
PGA
SPI INTERFACE
OUTPUT
DRIVERS
SYSTEM
REFERENCE AND
POWER
MANAGEMENT
ERROR
CORRECTION AND
DIGITAL
PROCESSING
ADC CORE
14-BIT
PIPELINED
S/H
INPUT
STAGE
INP
OTR
PWD
CMOS:
D13 to D0
or
LVDS/DDR:
D13P, D13M
to D0P, D0M
INM
CLOCK INPUT
STAGE AND DUTY
CYCLE CONTROL
005aaa101
OE
INPUT
BUFFER
CMOS:
DAV
or
LVDS/DDR:
DAVP
DAVM


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