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ADC1610S125 Arkusz danych(PDF) 9 Page - NXP Semiconductors

Numer części ADC1610S125
Szczegółowy opis  Single 16-bit ADC 125 Msps CMOS or LVDS DDR digital outputs
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Producent  NXP [NXP Semiconductors]
Strona internetowa  http://www.nxp.com
Logo NXP - NXP Semiconductors

ADC1610S125 Arkusz danych(HTML) 9 Page - NXP Semiconductors

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ADC1610S125_1
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 — 28 May 2009
9 of 33
NXP Semiconductors
ADC1610S125
Single 16-bit ADC 125 Msps
10.2 Clock and digital output timing
[1]
Measured between 20 % to 80 % of VDDO; rise time measured from −50 mV to +50 mV; fall time measured from +50mV to −50mV.
10.3 SPI timings
Table 8.
Dynamic characteristics
Typical values measured at VDDA =3V, VDDO = 1.8 V, Tamb =25 °C and CL = 5 pF; min. and max. values are across the full
temperature range Tamb = −40 °C to +85 °C at VDDA =3V, VDDO = 1.8 V; VINP − VINM = −1 dBFS; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Clock timing input: pins CLKP and CLKM
fclk
clock frequency
60
-
125
MHz
tlat(data)
data latency time
-
14
-
clk/cy
δclk
clock duty cycle
DCS_EN = 1
30
50
70
%
DCS_EN = 0
45
50
55
%
td(s)
sampling delay time
-
0.8
-
ns
twake
wake-up time
-
<tbd>
-
ns
CMOS mode timing output: pins D13 to D0 and DAV
tPD
propagation delay
DATA
-
3.9
-
ns
DAV
-
4.2
-
ns
tsu
set-up time
-
4.3
-
ns
th
hold time
-
3.5
-
ns
tr
rise time
DATA
[1] 0.5
-
2.4
ns
DAV
0.5
-
2.4
ns
tf
fall time
DATA
[1] 0.5
-
2.4
ns
LVDS DDR mode timing output: pins D13P, D13M to D0P, D0M, DAVP and DAVM
tPD
propagation delay
DATA
-
3.9
-
ns
DAV
-
4.2
-
ns
Table 9.
Characteristics
Typical values measured at VDDA =3V, VDDO = 1.8 V, Tamb =25 °C and CL = 5 pF.
Min. and max. values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA =3V, VDDO = 1.8 V
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SPI timings
tw(SCLK)
SCLK pulse width
40
-
-
ns
tw(SCLKH)
SCLK HIGH pulse width
16
-
-
ns
tw(SCLKL)
SCLK LOW pulse width
16
-
-
ns
tsu
set-up time
data to SCLKH
5
-
-
ns
CS to SCLKH
5
-
-
ns
th
hold time
data to SCLKH
2
-
-
ns
CS to SCLKH
2
-
-
ns
fclk(max)
maximum clock frequency
-
-
25
MHz


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