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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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ADXRS450 Arkusz danych(PDF) 21 Page - Analog Devices |
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ADXRS450 Arkusz danych(HTML) 21 Page - Analog Devices |
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21 / 28 page  ADXRS450 Rev. 0 | Page 21 of 28 MEMORY REGISTER DEFINITIONS The SPI accessible memory registers are described in this section. As explained in the previous section, when requesting data from a memory register, only the first sequential memory address need be addressed. The data returned by the device contain 16 bits of memory register information. Bits[15:8] contain the MSB of the requested information, and Bits[7:0] contain the LSB. Rate Registers Addresses: 0x00 (RATE1) 0x01 (RATE0) Register update rate: 500 Hz Scale factor: 80 LSB/°/sec The rate registers contain the temperature compensated rate output of the device filtered to 80 Hz. This data can also be accessed by issuing a sensor data read request to the device. The data is pre- sented as a 16-bit, twos complement number. MSB LSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Temperature (TEMx) Registers Addresses: 0x02 (TEM1), 0x03 (TEM0) Register update rate: 500 Hz Scale factor: 5 LSB/°C The TEM register contains a value corresponding to the temper- ature of the device. The data is presented as a 10-bit, twos complement number. 0 LSB corresponds to a temperature of approximately 45°C. MSB LSB D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (Unused) Table 16. Temperature Value of TEM1:TEM0 45°C 0000 0000 00XX XXXX 85°C 0011 0010 00XX XXXX 0°C 1100 0111 11XX XXXX Low CST (LOCST) Memory Registers Addresses: 0x04 (LOCST1) 0x05 (LOCST0) Register update rate: 1000 Hz Scale factor: 80 LSB/°/sec The LOCST memory registers contain the value of the temperature compensated and low-pass filtered continuous self-test delta. This value is a measure of the difference between the positive and negative self-test deflections and corresponds to the values presented in Table 1. The device issues a CST error if the value of self-test exceeds the established self-test limits. The self-test data is filtered to 2 Hz to prevent false triggering of the CST fault bit. The data is presented as a 16-bit, twos complement number, with a scale factor of 80 LSB/°/sec. MSB LSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 High CST (HICST) Memory Registers Addresses: 0x06 (HICST1), 0x07 (HICST0) Register update rate: 1000 Hz Scale factor: 80 LSB/°/sec The HICST register contains the unfiltered self-test information. The HICST data can be used to supplement fault diagnosis in safety critical applications as sudden shifts in the self-test response can be detected. However, the CST bit of the fault register is not set when the HICST data is observed to exceed the self-test limits. Only the LOCST memory registers, which are designed to filter noise and the effects of sudden temporary self-test spiking due to external disturbances, control the assertion of the CST fault bit. The data is presented as a 16-bit, twos complement number. MSB LSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Quad Memory Registers Addresses: 0x08 (QUAD1) 0x09 (QUAD0) Register update rate: 250 Hz Scale factor: 80 LSB/°/sec equivalent The quad memory registers contain a value corresponding to the amount of quadrature error present in the device at a given time. Quadrature can be likened to a measurement of the error of the motion of the resonator structure, and can be caused by stresses and aging effects. The quadrature data is filtered to 80 Hz and can be read frequently to detect sudden shifts in the level of quadrature. The data is presented as a 16-bit, twos complement number. MSB LSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 |
Podobny numer części - ADXRS450_11 |
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Podobny opis - ADXRS450_11 |
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