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LC72709E Arkusz danych(PDF) 8 Page - Sanyo Semicon Device |
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LC72709E Arkusz danych(HTML) 8 Page - Sanyo Semicon Device |
8 / 16 page No. 5876-8/16 LC72709E, 72709W Detailed Descriptions • VEC HALT Setting this flag stops all IC operations related to vertical and second horizontal correction. Data output is limited to data following the first horizontal correction. • EC STOP This flag stops all operations (including RAM access) related to error correction and all data output operations. While all IC operations are stopped in standby mode, MSK demodulation, the synchronization circuit, the serial data input circuit, and the layer 4 CRC circuit continue to operate in this mode. • SYNC RST Clears the synchronization state and the synchronization protection state in the synchronization block and sets that block to the unsynchronized state. This allows quick frame synchronization pull in when, during receiver tuning operations, the frame period of the new reception data after station selection is displaced. While this flag is used for initialization of synchronization related circuits, it does not initialize the number of allowed BIC errors, the block synchronization forward and backward protection settings, and the registers of frame synchronization forward and backward protection settings. During the synchronization block reset, the INT signal is not output and the DO pin outputs a high level (high impedance). Since this flag is not automatically reset to 0, applications must send data again to set it to 0. • INT MOVE The data output by this IC is fully corrected, and only data received during both block and frame synchronization is output. (The layer 2 CRC check is included.) This flag must be set to acquire all data in the same manner as the LC72700. • DO MOVE In the LC72700, the DO pin output was linked to and changed with the INT signal so that it could be used in place of the INT CPU interrupt signal. Set this flag to use that function. • RTIB In the method A frame structure in the ITU-R recommendations, a total of 12 data blocks have been inserted in the parity data area, in which the 82 consecutive blocks of parity information are held. This flag must be set if this IC is used in systems that do not have these real-time information blocks (RTIB). Note that if the state of this flag is changed, frame synchronization will be held for the time corresponding to the forward protection count and then will switch to the unsynchronized state. Applications must use the SYNC RST flag to reset the synchronization circuit to reestablish frame synchronization more quickly. Control Register Control register FRAME RTIB VEC HALT EC STOP SYNC RST INT MOVE DO MOVE CRC4 RST 0 1 2 3 4 5 6 7 Bit Function Initial value 0 FRAME L Method-B L (Frame selection) H Method-A 1 RTIB L Real-time information blocks present (When method A is selected) L (RTIB presence) H No real-time information blocks present (When method A is selected) 2 VEC HALT L Vertical correction and second horizontal correction: enabled L (Vertical error correction stop) H Vertical correction and second horizontal correction: disabled 3 EC STOP L All functions operate L (Error correction stop) H Only the MSK detection and synchronization regeneration circuits operate 4 SYNC RST L L (Synchronization block reset) H Only the synchronization circuit is reset 5 INT MOVE L Only the correction complete, layer 2 CRC complete, and data received while synchronized are output. L (INT type) H All data is output. (Operation identical to that of the LC72700) 6 DO MOVE L The high-level (high-impedance) state is held at times other than data output L (DO pin operation) H The DO pin changes with the INT pin. (Operation identical to that of the LC72700) 7 CRC4 RST L L (Layer 4 CRC) H The layer 4 CRC circuit is reset to its initial state. |
Podobny numer części - LC72709E |
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Podobny opis - LC72709E |
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