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LC74760M Arkusz danych(PDF) 8 Page - Sanyo Semicon Device |
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LC74760M Arkusz danych(HTML) 8 Page - Sanyo Semicon Device |
8 / 14 page 3 COMMAND2: Vertical Display Position Setting Command First byte Register content DA0 to DA7 Register name State Function Note 7 — 1 6 — 0 The command 2 identification code: 5 — 1 sets the vertical display position. 4 — 0 3 SZ21 0 1 Character size for the second line 2 SZ20 0 1 1 SZ11 0 1 Character size for the first line 0 SZ10 0 1 Second byte Register content DA0 to DA7 Register name State Function Note 7 — 0 Second byte identification code 6 — 0 5 VP5 0 The vertical display start position is given by (MSB) 1 4 VP4 0 1 where H is the horizontal synchronization pulse period. 3 VP3 0 The six bits VP0 to VP5 specify the 1 vertical display start position. 2 VP2 0 The weight of the lsb is 1 × H. 1 1 VP1 0 1 0 VP0 0 (LSB) 1 Note: When the chip is reset by the RST pin, the register states (bits) are all cleared to 0. 4 COMMAND3: Horizontal Display Position Setting Command First byte Register content DA0 to DA7 Register name State Function Note 7 — 1 6 — 0 The command 3 identification code: 5 — 1 sets the horizontal display position. 4 — 1 3 SZB1 0 1 The character size for the eleventh line. 2 SZB0 0 1 1 SZ91 0 1 The character size for the ninth line. 0 SZ90 0 1 No. 4453-8/14 LC74760, 74760M SZ20 SZ21 0 1 0 Normal size Double size 1 Triple size Normal size SZ10 SZ11 0 1 0 Normal size Double size 1 Triple size Normal size SZB0 SZB1 0 1 0 Normal size Double size 1 Triple size Normal size SZ90 SZ91 0 1 0 Normal size Double size 1 Triple size Normal size 5 VS = H × ( Σ 2nVPn) n = 0 |
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