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LC78625 Arkusz danych(PDF) 20 Page - Sanyo Semicon Device

Numer części LC78625
Szczegółowy opis  Compact Disc Player DSP
Download  35 Pages
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Producent  SANYO [Sanyo Semicon Device]
Strona internetowa  https://www.sanyo-av.com/us/
Logo SANYO - Sanyo Semicon Device

LC78625 Arkusz danych(HTML) 20 Page - Sanyo Semicon Device

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No. 5502-20/35
LC78625E
Note:*When the desired track count has been input in binary, the track check operation is started by the fall of RWC.
* During a track check operation the TOFF pin goes high and the tracking loop is turned off. Therefore, feed motor forwarding is required.
* When a track check in/out command is issued the function of the WRQ signal switches from the normal mode subcode Q standby monitor function to
the track check monitor function. This signal goes high when the track check is half completed, and goes low when the check finishes. The control
microprocessor should monitor this signal for a low level to determine when the track check completes.
* If a two-byte reset command is not issued, the track check operation will repeat. That is, to skip over 20,000 tracks, issue a track check 201 command
once, and then count the WRQ signal 100 times. This will check 20,000 tracks.
* After performing a track check operation, use the brake command to have the pickup lock onto the track.
9. Error flag output; Pin 58: EFLG, pin 62: FSX
The FSX signal is generated by dividing the crystal oscillator clock, and is a 7.35 kHz frame synchronization signal.
The error correction state for each frame is output from EFLG. The playback OK/NG state can be easily determined
from the extent of the high level that appears here.
10. Subcode P, Q, and R to W output circuit; Pin 59: PW, pin 57: SBSY, pin 60: SFSY, pin 61: SBCK
PW is the subcode signal output pin, and all the codes, P, Q, and R to W can be read out by sending eight clocks to
the SBCK pin within 136 µs after the fall of SFSY. The signal that appears on the PW pin changes on the rising edge
of SBCK. If a clock is not applied to SBCK, the P code will be output from PW. SFSY is a signal that is output for
each subcode frame cycle, and the falling edge of this signal indicates standby for the output of the subcode symbol
(P to W). Subcode data P is output on the fall of this signal.
SBSY is a signal output for each subcode block. This signal goes high for the S0 and S1 synchronization signals. The
fall of this signal indicates the end of the subcode synchronization signals and the start of the data in the subcode
block. (EIAJ format)


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