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LC78628 Arkusz danych(PDF) 28 Page - Sanyo Semicon Device |
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LC78628 Arkusz danych(HTML) 28 Page - Sanyo Semicon Device |
28 / 40 page No. 6329-28/40 LC78628E XDSEL DIN16 Input source signal to the HDCD filter block RES = low 00 HDCD decoder block 20-bit output data q q 01 1 0 20-bit data input to the LRCKI, BCKI, DATAI, and EMPH pins 1 1 16-bit data input to the LRCKI, BCKI, DATAI, and EMPH pins 1/352.8 kHz Normal speed: 1/44.1 kHz, 2 × speed: 1/88.2 kHz Rch 2 1 MSB 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 MSB 18 17 16 15 14 13 12 11 10 987654321 LSB 2 1 18 LSB MSB LSB LSB LSB MSB MSB 1716151413121110 9 8 7 6 5 4 3 2 1 LSB MSB 18171615 13 14 121110 9 8 7 6 5 4 3 2 1 LSB Lch DFORO DFOLO LRCKO DACKO DFORO DFOLO LRCKO DACKO A12827 A12828 • Timing when 1FSOUT is 0 • Timing when 1FSOUT is 1 HDCD Filter Processed Signal Output to the D/A Converter Block The 8 × oversampled data (4 × oversampled in double-speed playback) processed by the HDCD filter block is transferred to the internal D/A converter block, converted to PWM data, and output from the LCHP, LCHN, RCHN, and RCHP pins. This 8 × oversampling filter output signal has had internal deemphasis filtering and attenuator processing applied. HDCD Filter Block Source Switching — Pin 57: LRCKI, pin 61: BCKI, pin 59: DATAI, pins 32: EMPH The signal to be processed in the HDCD filter block can be set to be either the 20-bit data from the HDCD decoder block or external data with the XDSETL flag in the HDCD control register. If data input from outside the IC is selected as the HDCD filter block source signal, the bit length of that data (i.e. the serial input format) can be switched as shown in the table below using the DIN16 flag in the HDCD control register. |
Podobny numer części - LC78628 |
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Podobny opis - LC78628 |
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