Block Diagram

• CPU interface

This circuit is a general-purpose 8-bit CPU interface. The operating mode and other aspects are set by accessing the

interface registers and the parameter registers.

• Sequence controller

Controls the functional blocks in the IC according to the encoding or decoding algorithm being used.

• Encoder

Generates the codes in the various modes by recognizing inflection points in the image data. Encoded data is passed to

the data bus through an 8-bit 4-word encoding FIFO (EFIFO).

• Decoder

Recognizes the codes in the various modes and recovers the original image data. Image data is passed to the data bus

through a decoding FIFO (DFIFO).

• Image bus interface

Controls reads from and writes to image memory as well as DMA transfers on the image memory bus.

No. 5753-2/5

LC8213K

Parameter

Symbol

Conditions

Ratings

Unit

min

typ

max

Supply voltage

4.5

5.0

5.5

V

Input voltage range

0

V

Parameter

Symbol

Conditions

Ratings

Unit

min

typ

max

Input high-level voltage

2.2

V

Input low-level voltage

0.8

V

Input leakage current

–10

+10

µA

Output high-level voltage

2.4

V

Output low-level voltage

0.4

V

Output leakage current

For pins in the high-impedance output state

–10

+10

µA

Input clock frequency

CLK

25

MHz

Current drain

10

20

mA

A2 to A0

D7 to D0

TEST4 to TEST0

MA23 to MA16

MA/MD15 to MA/MD0