LC875164A/48A/32A

No.6715-3/25

(10) Remote control receiver circuit (connected to P73/INT3/T0IN terminal)

(11) Watchdog timer

- The watchdog timer period set by external RC.

- Watchdog timer can be set to produce interrupt, system reset

(12) Interrupts

- 19-source, 10-vectored interrupts:

1. Three level (low, high and highest) multiple interrupts are supported. During interrupt handling, an equal or

lower level interrupt request is refused.

2. If interrupt requests to two or more vector addresses occur at once, the higher level interrupt takes precedence.

In the case of equal priority levels, the vector with the lowest address takes precedence.

No.

Vector

Selectable Level

Interrupt signal

1

00003H

X or L

INT0

2

0000BH

X or L

INT1

3

00013H

H or L

INT2/T0L/INT4

4

0001BH

H or L

INT3/INT5/Base timer

5

00023H

H or L

T0H

6

0002BH

H or L

T1L/T1H

7

00033H

H or L

SIO0

8

0003BH

H or L

SIO1/SIO2

9

00043H

H or L

ADC

10

0004BH

H or L

Port 0/T4/T5/PWM0, 1

• Priority Level : X > H > L

• For equal priority levels, vector with lowest address takes precedence.

(13) Subroutine stack levels

- 512 levels max. Stack is located in RAM

(14) Multiplication and division

- 16 bit

× 8 bit

(executed in 5 cycles)

- 24 bit

× 16 bit

(12 cycles )

- 16 bit ÷ 8 bit

(8 cycles)

- 24 bit ÷ 16 bit

(12 cycles)

(15) Oscillation circuits

- On-chip RC oscillation circuit used for system clock

- On-chip CF oscillation circuit used for system clock

- On-chip Crystal oscillation circuit used for system clock and time-base clock

(16) Standby function

- HALT mode

HALT mode is used to reduce power consumption. Program execution is stopped. Peripheral circuits still operate.

1. Oscillation circuits are not stopped automatically

2. Release on system reset

- HOLD mode

HOLD mode is used to reduce the power dissipation. Both program execution and peripheral circuits are stopped.

1. CF, RC and crystal oscillation circuits stop automatically

2. Release occurs on any of the following conditions

•input to the reset pin goes low

•a specified level is input to at least one of INT0, INT1, INT2, INT4, INT5

•an interrupt condition arises at port 0